I am working on making a second level cache for microbalze processor on a ML403 board. This comes in the virtex-4 family. I am looking at32KB space for cache data. The tag stays in a separate block. The problem that I am having here is that each BRAM primitive is of 2KB, hence i am in an uncomfortable situation in which I would have to use 16 different variables.
Is there a way in which I can combine the 16 primitives and get a 32Kb block ram? If so, please specify some details and some links which have information regarding the same.
Thanks in advance,