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Interfacing to 10Gig ethernet with Xilinx FPGAs

Hello there, I have a query for the more knowledgeable than me.. We've been playing quite successfully with 1 gig Ethernet in our labs that we're getting bold and want to move to 10Gig.

I was wondering if anyone else had experience of the various phy layer transceivers that are available. We're about to sign the NDA's for Marvell, Vitesse and Broadcom (if they ever get back to me....) so we can get details on the various chips. But helpful hints from anyone here would be nice..

The 10gig side will probably be an XFP interface cage, as we have a couple of 10gig PCIexpress NICs that use those. Stealing an XPF fibre module from that side of the lab is the easy part *wink*

I saw a powerpoint with info on the Xilinx RocketPHY chip, does that still exist?? The links I tried all refused to work..

Our current board (Virtex4FX60 based, it has PCIexpress connector for going into an 8lane socket, and also has a 4lane socket on it for adding additional PCIexpress cards to it. ) has a nice samtec connector array with at least 20 TX and 20 RX pairs on it which we're thinking of using for the XSBI style interface, it has also got a fair number of single ended connections for the slower management stuff as well.

We also have available 4 rocket IOs, however these come out via the top PCIexpress motherboard style socket on the board. Our friendly pcb designer laughs at the prospect of doing XAUI over those. It's the kind of laugh that says "go away you firmware man and bother me not with such crazy ideas" I am guessing he's probably correct?

Also, anyone played/experienced the Xilinx 10Gig MAC IPCore?

Before anyone asks, we're not building a NIC, but a novel high energy physics R&D project for a DAQ system..

Cheers...

--
/\/\arc Kelly
..Just your average physicist trying to get by in a world full of normal
people...
Reply to
Marc Kelly
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Marc,

The 10G MGTs are all discontinued.

Anyone who had alrewady designed them in is supported.

But, there are no new orders accepted.

The issue was that the rate (10Gbs) was just too demanding for the design and technology. By that, I mean yield of the final chips was unacceptable. All MGTs had to work at all rates, over all temperatures, with the exact same bit settings.

10 Gbs also was a very tiny market segment (only a handful wanted it at all).

The hard part was that on any given chip, all MGTs would work well out to 13.5 Gbs, but they each required slightly different bit settings.

This required significant soft IP to find the settings for each MGT. It was not considered a viable solution for the mass market. Someday when we harden this IP, and re-design for the next generation, and more than just a few customers require it, 10 Gbs (+) will re-appear.

Until then, the separate phy chips are the best solution.

Austin

Reply to
Austin

Hi Marc

The VSC8479 (Vittesse) chip works fine as weel the Xilinx 10Gig MAC IPCore. We use both.

Cheers...

Reply to
Alain

That has been my thinking, one of my current candidates is

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we're having to wait for our university management to sign the NDA required to get full data sheets, but it looks promising.

I am presuming the V4 should cope with the 644Mhz for the XSBI interface? Or is that pushing things a bit too much for a V4 and its best to see if we can get a V5 development board to do this with?

Am slightly regretting the decision to say we could do 10Gig easily, our networking people are too obsessed with more and more speed... :)

--
/\/\arc Kelly
..Just your average physicist trying to get by in a world full of normal
people...
Reply to
Marc Kelly

Hi Marc,

Virtex-4 is enough for 10Gig but Virtex-5 has interesting feature like OSERDES.

Reply to
Alain

Nice, that is the one I have been looking at.. So knowing someone else has it working makes me slightly more confident I am not totally bull****ing my bosses :)

Cheers for that

--
/\/\arc Kelly
..Just your average physicist trying to get by in a world full of normal
people...
Reply to
Marc Kelly

Just curious if anyone knows any facts/rumors about any eval boards (like, say an ML403) that are 10G capable?

Reply to
Jeff Cunningham

Speaking of fast networking with Xilinx FPGAs: I've read about getting

780MByte/s via TCP/IP using a Virtex4 with the stack from treck.com. That should be fast enough for our current development. But in case we need more in future, any idea how to implement this on a Xilinx FPGA?

Greetings, Torsten

Reply to
Torsten Landschoff

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