Field-Programmable Gate Arrays

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Xilinx programmer, many unknown devices...

I would like to ask some questions regarding a Xilinx JTAG programmer: First, it seems that the programmer doesn't actu...
9 comments posted 19yrs
posted by <darrick>
9 comments posted 19yrs posted by <darrick>

Virtex5 LXT Clock Distribution

I am using four GTP transceivers of V5 LXT 110T FPGA. I used coregen to create the verilog output. When I looked at the...
0 comments posted 19yrs
posted by
0 comments posted 19yrs posted by

Interfacing a camera to a fpga

Hello everybody, I am trying to connect a 2 Meg pixel PixelPlus camera with a XUPV2P board based on Virtex 2P. The came...
0 comments posted 19yrs
posted by koustav79
0 comments posted 19yrs posted by koustav79

Xilinx ngdbuild question

Hi, I use Coregen (CORE Generator of Xilinx) to generate a fifo and I get .ngc. How do I specify this in ngdbuild comma...
3 comments posted 19yrs
posted by chinchia.kuo
3 comments posted 19yrs posted by chinchia.kuo

Latches

This document is formatted in Rich Text (html). It contains a couple of images (ascii art). If you read it as plain text...
8 comments posted 19yrs
posted by me
8 comments posted 19yrs posted by me

How to snoop an inout signal in EDK?

For example, signal A is an inout signal of certain IP and connected to an external pin of the FPGA with a net(let's ca...
1 comments posted 19yrs
posted by lipeng.net
1 comments posted 19yrs posted by lipeng.net

Execute from SPI flash

Execute from SPI flash has always appealed as one way to reduce the PCB cost of the Code memory needed by Soft CPUs. Wi...
3 comments posted 19yrs
posted by no.spam
3 comments posted 19yrs posted by no.spam

modelsim search path

Does any one know how to set the search path so my modelsim pe 6.0c will find the .mif file associated with my coregen...
5 comments posted 19yrs
posted by cepope
5 comments posted 19yrs posted by cepope

d-link router?

Does anyone know which cpu do they use in the d-link router/adsl modem dsl-g624t ? Aparently, they are running linux in...
5 comments posted 19yrs
posted by <len>
5 comments posted 19yrs posted by <len>

vista 64 bits

hi Xilinx, i had a look at ISE 9.2 today. It's supporting Vista 32 bits. When should we have a Vista 64 bits support ? r...
4 comments posted 19yrs
posted by christophe.alexandre
4 comments posted 19yrs posted by christophe.alexandre

USB JTAG Programming

I'm looking at adding an embedded USB JTAG programmer onto our latest board, and am just looking for a bit of advice. T...
6 comments posted 19yrs
posted by neilla
6 comments posted 19yrs posted by neilla

How to write constraints with a clock enable?

Hello, lets take this verilog example snipplet reg clk_en; reg [:0] wide_reg; always @(posedge clk) begin clk_en
1 comments posted 19yrs
posted by bon
1 comments posted 19yrs posted by bon

ISE 9.1 Problem

Hi Can anyone tell me what Xilinx have done to the timing summary in ISE 9.1 In 8.2 it used to give you what you reques...
0 comments posted 19yrs
posted by maxascent
0 comments posted 19yrs posted by maxascent

Xilinx FPGA to interface to special I/O

I have a specific application where the FPGA needs to generate SPI bus like interface to a device but at different elec...
16 comments posted 19yrs
posted by
16 comments posted 19yrs posted by