Field-Programmable Gate Arrays

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Bidirectional LVDS

I need to extend a memory-mapped bus into another enclosure and thought that a bidirectional LVDS implementation with s...
11 comments posted 19yrs
posted by pomerado
11 comments posted 19yrs posted by pomerado

EDK Custom IP

I am trying to add a custom IP to my EDK project. I am using the Avnet Mini-Module (MM) and EDK 9.1i SP2. This is my fi...
1 comments posted 19yrs
posted by SWAmdata
1 comments posted 19yrs posted by SWAmdata

Adding opb AC97 Controler in Xilinx EDK 8.2

Hi all, I am facing a problem. I cannot find the opb AC97 Controler in BSB, EDK 8.2 to add to my project. I am new to E...
1 comments posted 19yrs
posted by dineshvc
1 comments posted 19yrs posted by dineshvc

Virtex4 ISERDES question

I am simulating a verilog design that uses Virtx4 ISERDES primitive. This design requires the "O" ouput pin of the Virt...
0 comments posted 19yrs
posted by
0 comments posted 19yrs posted by

CameraLink to Hotlink-II video converter

Hi All, We are looking for a board (or adaptor) able to convert CameraLink video to Hotlink-II. Thanks in advance, Rotem
2 comments posted 19yrs
posted by rotem.gazit
2 comments posted 19yrs posted by rotem.gazit

Can FPGAs inputs detect low currents?

Hello I'm new to FPGAs. I need some kind of 30-40 channel input extension beeing able to detect 0.01mA currents. (The c...
5 comments posted 19yrs
posted by marco-oweber
5 comments posted 19yrs posted by marco-oweber

regarding the montavista linux preview kit

Dear all, I am working on Virtex-4 Fx12LC (ML 403 ) Fpga that has powerpc hard core. I would want to load Linux RTOS on...
1 comments posted 19yrs
posted by mouli1982
1 comments posted 19yrs posted by mouli1982

Xilinx ISE 9.1 - Version Control - VSS

Greetings, Has anyone used Microsoft Visual Source Safe or any other software version control applications to manage IS...
6 comments posted 19yrs
posted by jeremylees
6 comments posted 19yrs posted by jeremylees

what is speed grade in virtes1

wht means speedgrade in xilinx fpgas? what rold speed grade plays in the design and selection of fpga for a design? If...
0 comments posted 19yrs
posted by vkmselva
0 comments posted 19yrs posted by vkmselva

Amontec chameleon

Hello Amontec, Larry, Spefically for you, since I did not get any reposone from the Amontec site! Could you explain the...
2 comments posted 19yrs
posted by ravishankar.s
2 comments posted 19yrs posted by ravishankar.s

Trace capturing

Hello, Im in embedded software development, but interested in developing a device which can caputure trace information...
4 comments posted 19yrs
posted by ravishankar.s
4 comments posted 19yrs posted by ravishankar.s

Coding style of verilog for FPGA synthesis

hi, guys We design a hardware written in Verilog and synthesize by Synopsys Design Vision. The post-synthesis simulatio...
5 comments posted 19yrs
posted by lphplab
5 comments posted 19yrs posted by lphplab