Latest threads in Field-Programmable Gate Arrays

Xilinx Modelsim XE-III 6.2g no more Systemverilog support?

I upgraded my Modelsim XE-III 6.2c starter edition to Modelsm XE-III 6.2g starter edition. Before isntalling the new so...

4 19yrs

anonymous

4 19yrs anonymous

Bit error counter - how to make it faster

My goal is to implement a bit-error counter targeting 1GHz. The datawidth is parametrizable. I started off this way, Ve...

10 19yrs

csanjay

10 19yrs csanjay

Bidirectional LVDS

I need to extend a memory-mapped bus into another enclosure and thought that a bidirectional LVDS implementation with s...

11 19yrs

pomerado

11 19yrs pomerado

EDK Custom IP

I am trying to add a custom IP to my EDK project. I am using the Avnet Mini-Module (MM) and EDK 9.1i SP2. This is my fi...

1 19yrs

SWAmdata

1 19yrs SWAmdata

VHDL and Verilog - 15 x Contract Engineers Required Urgently - Long Term Contract

My client is an award winning leader in their global field, and looking to expand their broadcast engineering team. If...

0 19yrs

reast

0 19yrs reast

Adding opb AC97 Controler in Xilinx EDK 8.2

Hi all, I am facing a problem. I cannot find the opb AC97 Controler in BSB, EDK 8.2 to add to my project. I am new to E...

1 19yrs

dineshvc

1 19yrs dineshvc

A strange error during PAR process in EDK, could anyone in xilinx help me?

The device is v4fx60-ES. EDK and ISE versions are 9.1.02 and 9.1.03 seprately. The error message apears as follows: Pha...

5 19yrs

lipeng.net

5 19yrs lipeng.net

Virtex4 ISERDES question

I am simulating a verilog design that uses Virtx4 ISERDES primitive. This design requires the "O" ouput pin of the Virt...

0 19yrs

CameraLink to Hotlink-II video converter

Hi All, We are looking for a board (or adaptor) able to convert CameraLink video to Hotlink-II. Thanks in advance, Rotem

2 19yrs

rotem.gazit

2 19yrs rotem.gazit

Can FPGAs inputs detect low currents?

Hello I'm new to FPGAs. I need some kind of 30-40 channel input extension beeing able to detect 0.01mA currents. (The c...

5 19yrs

marco-oweber

5 19yrs marco-oweber

regarding the montavista linux preview kit

Dear all, I am working on Virtex-4 Fx12LC (ML 403 ) Fpga that has powerpc hard core. I would want to load Linux RTOS on...

1 19yrs

mouli1982

1 19yrs mouli1982

Xilinx ISE 9.1 - Version Control - VSS

Greetings, Has anyone used Microsoft Visual Source Safe or any other software version control applications to manage IS...

6 19yrs

jeremylees

6 19yrs jeremylees

what is speed grade in virtes1

wht means speedgrade in xilinx fpgas? what rold speed grade plays in the design and selection of fpga for a design? If...

0 19yrs

vkmselva

0 19yrs vkmselva

Amontec chameleon

Hello Amontec, Larry, Spefically for you, since I did not get any reposone from the Amontec site! Could you explain the...

2 19yrs

ravishankar.s

2 19yrs ravishankar.s

Trace capturing

Hello, Im in embedded software development, but interested in developing a device which can caputure trace information...

4 19yrs

ravishankar.s

4 19yrs ravishankar.s

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