modelsim search path

Jun 29, 2007 5 Replies

Does any one know how to set the search path so my modelsim pe 6.0c will find the .mif file associated with my coregen blocks? I get the following error:



# Loading C:/Xilinx/vhdl/mti_pe/XilinxCoreLib.cordic_v3_0(behavioral) # ** Error: (vsim-7) Failed to open VHDL file "dds_SINCOS_TABLE_TRIG_ROM.mif" in rb mode. # No such file or directory. (errno = ENOENT) # Time: 0 ns Iteration: 0 Instance: /ddr_9479_tb/uut/bfo_g1/nco/bu273 # ** Fatal: (vsim-7) Failed to open VHDL file "dds_SINCOS_TABLE_TRIG_ROM.mif" in rb mode. # No such file or directory. (errno = ENOENT) # Time: 0 ns Iteration: 0 Process: /ddr_9479_tb/uut/bfo_g1/nco/bu273/dp_primitive File: C:/Xilinx/vhdl/mti_pe/XilinxCoreLib/XilinxCoreLib_source.vhd # Fatal error at C:/Xilinx/vhdl/mti_pe/XilinxCoreLib/XilinxCoreLib_source.vhd line 80173



If I copy the .mif to the root directory it works okay, but I want to keep my top module and test bench one directory up from the subblocks.



Thanks, Clark


The mif file might be specified as a generic in your vhd wrapper file, change the path, recompile and bob's your uncle :-)

Hans

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"HT-Lab" wrote in message news:%E2hi.8371$ snipped-for-privacy@newsfe2-gui.ntli.net...

following

/ddr_9479_tb/uut/bfo_g1/nco/bu273

keep

You mean change in dds.vhd, for example, (see below)? Wouldn't that mean I have to edit everytime I regenerate that core?

BU273 : blkmemdp_v6_0 GENERIC MAP ( c_reg_inputsb => 0, c_reg_inputsa => 0, c_has_ndb => 0, c_has_nda => 0, c_ytop_addr => "1024", c_has_rfdb => 0, c_has_rfda => 0, c_ywea_is_high => 1, c_yena_is_high => 1, c_yhierarchy => "hierarchy1", c_yclka_is_rising => 1, c_ysinita_is_high => 1, c_ybottom_addr => "0", c_width_b => 10, c_width_a => 10, c_sinita_value => "0000", c_sinitb_value => "0000", c_limit_data_pitch => 18, c_write_modeb => 0, c_write_modea => 0, c_has_rdyb => 0, c_yuse_single_primitive => 0, c_has_rdya => 0, c_addra_width => 10, c_addrb_width => 10, c_has_limit_data_pitch => 0, c_default_data => "0000", c_pipe_stages_b => 0, c_yweb_is_high => 1, c_yenb_is_high => 1, c_pipe_stages_a => 0, c_yclkb_is_rising => 1, c_yydisable_warnings => 1, c_enable_rlocs => 0, c_ysinitb_is_high => 1, c_has_web => 0, c_has_default_data => 0, c_has_wea => 0, c_has_sinitb => 0, c_has_sinita => 0, c_has_dinb => 0, c_has_dina => 0, c_ymake_bmm => 0, c_has_enb => 1, c_has_ena => 1, c_mem_init_file => "dds_SINCOS_TABLE_TRIG_ROM.mif", c_depth_b => 1024, c_depth_a => 1024, c_has_doutb => 1, c_has_douta => 1, c_yprimitive_type => "4kx4" ) PORT MAP ( addra => BU273_addra, addrb => BU273_addrb, clka => BU273_clka, clkb => BU273_clkb, dina => BU273_dina, dinb => BU273_dinb, douta => BU273_douta, doutb => BU273_doutb, ena => BU273_ena, enb => BU273_enb, nda => BU273_nda, ndb => BU273_ndb, rfda => BU273_rfda, rfdb => BU273_rfdb, rdya => BU273_rdya, rdyb => BU273_rdyb, sinita => BU273_sinita, sinitb => BU273_sinitb, wea => BU273_wea, web => BU273_web );

snip

Yes, but how often do you re-generate your core(s)?

c_mem_init_file => "/dds_SINCOS_TABLE_TRIG_ROM.mif",

Regards, Hans.

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Every time you "build" from scratch (you can run coregen -b dds_SINCOS_TABLE_TRIG_ROM.xco and only check in the .xco and .coe files), or if you change ISE version, or if you change core parameters. And I agree its painful to edit auto generated files. I use "sed" to cut and paste in the generated file.

Modelsim seems to resolve environment variables in this case, so you can write: (the environment variable is resolved at elaboration, not compilation!)

c_mem_init_file => "$MY_SUBMODULE_PATH/coregen/ dds_SINCOS_TABLE_TRIG_ROM.mif"

I think the .mif file is only for simulation, but I might be wrong!? Do you know if the .mif file is ever used by ngdbuild?

Regards /Pontus

Probably easier for me to copy the .mif files up to the directory where I run the simulation. Would be nice if I could just add the subdirectory to the search path somehow.

I think you are right: .mif is only for simulation/coregen.

Thanks, Clark

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