Xilinx FPGA to interface to special I/O

I have a specific application where the FPGA needs to generate SPI bus like interface to a device but at different electrical voltage. SPI is a three wire serial bus interface I will be running at relatively slow speed of about 20MHz. The FPGA will drive out serial data out and serial clock out to the target device using lvcmos25 pudhpull driver and will be receiving serial data in.

The problem is that the traget device will have its vcc at 1.2V and and its Vee at -1.3V. As per my understanding FPGA can not drive out a waveform with 1.2v to

-1.3V swing. How to do the voltage translatin without affecting the signal integrity?

Any help will be greatly appreciated.

Albert.

Reply to
Albert Nguyen
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interface to a device but at different electrical voltage. SPI is a three wire serial bus interface I will be running at relatively slow speed of about 20MHz. The FPGA will drive out serial data out and serial clock out to the target device using lvcmos25 pudhpull driver and will be receiving serial data in.

Vee at -1.3V. As per my understanding FPGA can not drive out a waveform with

1.2v to -1.3V swing. How to do the voltage translatin without affecting the signal integrity?

Wow, that is one strange setup. What exists now, are Dual Vcc translators, but with your setup, probably the best device is something like this 90MBd isolator from ADI & -1.3V of gnd skew is nothing to this device :)

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-jg

Reply to
Jim Granville

interface to a device but at different electrical voltage. SPI is a three wire serial bus interface I will be running at relatively slow speed of about 20MHz. The FPGA will drive out serial data out and serial clock out to the target device using lvcmos25 pudhpull driver and will be receiving serial data in.

Vee at -1.3V. As per my understanding FPGA can not drive out a waveform with

1.2v to -1.3V swing. How to do the voltage translatin without affecting the signal integrity?

Often this kind of setup can be achieved by simply shifting your reference. If the "internal" circuitry can be changes to a 2.5V supply between -1.2V and +1.3V with no other ground-based reference, it's just a mental shift to get the right logic levels to/from the same places. If you have an external interface that's ground referenced in addition to your "split" supply, the technique won't work and level shifters will be needed.

Can you get by without ground-referenced I/O?

Reply to
John_H

Vee at -1.3V.

All SPI signals are unidirectional, so you should be able to level shift with a few transistors. Why not:

Vcc + | | 1k_ |< [SCK>---|___|--| |\ | o-------. .-. | | | | --- 500| | --- 10p "load" '-' | | o-------' | | === Vee

SCK high is > 1.2V, SCK low < 1.2V. Be sure to park SCK low, and invert the signals...

(created by AACircuit v1.28.6 beta 04/19/05

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--
Ben Jackson AD7GD

http://www.ben.com/
Reply to
Ben Jackson

John,

Thanks for you input. I looked at the ADUM1401 datasheet. So you are suggesting that on the FPGA side of this device, I connect the Vdd1 to 2.5 and Gnd1 to ground but on the other side of this device I connect the Vdd2 to +1.2 and GND2 to -1.3V. Is that correct?

Albert

Reply to
Albert Nguyen

Ben,

I am not able to see your picture clearly. I think that simple bipolar npn transistor can work if the biasing is done right. I am bit concerned about the rise time if the biaising is not done right.

Thanks.

Albert

Reply to
Albert Nguyen

John H,

The traget device will be running its VCC at 1.2V and Ground at -1.3V. Normally it will be running at 2.5 and 0 but in my application I need to run at +1.2V and

-1.3V in order to comply with the differential electrical specification. But in doing so, the sideband control pins (SPI Bus pins) electrical changes.

You asked if I can get by without ground reference I/O. Are you suggesting to connect the FPGA outputs SCLK and SERIAL DATA IN, directly to the target device?

If it is just a matter of scope probing then I can get by without ground reference i/o.

Thanks.

Albert

Reply to
Albert Nguyen

suggesting that on the FPGA side of this device, I connect the Vdd1 to 2.5 and Gnd1 to ground but on the other side of this device I connect the Vdd2 to +1.2 and GND2 to -1.3V. Is that correct?

Absolutely NOT my suggestion.

You want the FPGA to interface to those odd voltages. Hook the FPGA Vcco to +1.2V and the FPGA GND signals all to -1.3V. Just perform a mental shift of all FPGA voltaqes by 1.3V *IF* there are no other I/O that must interface as system ground referenced signals. If you can make *all* I/O a 2.5V swing relative to -1.3V, everything can flow.

If you have TTL signals going in one side from an external source and the +1.2/-1.3V signalling on the other side, you will need external signal translation. If your system is fully contained, there is no explicit need to make the ground reference for pushbutton-driven logic and the ground reference for the funky I/O levels of your unusual device the same potential.

All I'm suggesting is a mental shift of what "ground" is for an entire device. But only if it can be applicable to the entire device.

Reply to
John_H

Having FPGA VCC on 1.2V and GND on -1.3V is not possible as it affects many other FPGA signals.

Thanks.

Albert

Reply to
Albert Nguyen

Then you absolutely need level translators.

I feel I lost you on the idea of shifting your rails to a different absolute voltage while keeping all the rails and signals properly specified relative to each other. It may be your system doesn't need the absolute voltages you're planning. Since I don't know enough about your system to see if a compromise can be made, just design level translators.

You might look at using PNP transistors with a pull-down to -1.3V to provide the +1.2V to -1.3V swing.

Reply to
John_H

John,

I like your idea of using PNP trsistor with a -1.3V pulldown but I donot know how exactly I should be biasing the transistor. Especially the Base resistor and collector resistor values. It will be great if you can provide some details.

Thanks.

Albert

Reply to
Albert Nguyen

Please give an idea of your knowledge base. Are you a hardware engineer? Are you a software guy coming over to the "dark side?" Are you a hobbyist putting together your first "big" system? Do you have a soldering iron on the toolbelt you wear 10 hours a day?

The concepts of current gain, RC time constants, and transistor saturation work into the proper configuration along with cost and compliance issues.

You might be able to get by with a 2mA drive from a 1.2V rail depending on the common mode range you need to support. The signals are single ended, aren't they?

Reply to
John_H

suggesting that on the FPGA side of this device, I connect the Vdd1 to 2.5 and Gnd1 to ground but on the other side of this device I connect the Vdd2 to +1.2 and GND2 to -1.3V. Is that correct?

That was my suggestion, and yes. - but note the isolator is a 2.7V-5.5V device, so +ve could go to a slightly higher + rail in both cases.

Transistors are also usable, but they will struggle to get to your

20MHz, whilst the ADi devices spec 90MHz.

-jg

Reply to
Jim Granville

Select a fixed-width font like courier.

It's just a PNP transistor. The FPGA 0-3.3V swing can swing both high and low of the target's Vcc. You just have to scale the pulldown on the target side to the load capacitance of the receiving chip (that's why I showed a 10p "load").

Download LTspice and simulate it.

--
Ben Jackson AD7GD

http://www.ben.com/
Reply to
Ben Jackson

Ben,

I did a little reading on the bipolar transistors and made some calculations to figure out the base resistor value. But my caluclation does not match the base resistor value of 1K.

Icollecor = (1.2-(-1.3))/500

= 2.5/500

= 5 mA

IBase = 0.7/28.6 = 0.0244 Amps

If the FPGA is driving 3.3V signal then

Rbase = (3.3 - 0.7)/0.0244

= 106 Ohm.

You mentioned about using 1K Ohm base resistor but as per my calucaltion it needs to be about 106 Ohms if the FPGA is driving 0 to 3.3V signals.

Thus Rcollector = 500 Ohms and R base = 106 Ohms.

Does this make sense?

Thanks.

Albert

Reply to
Albert Nguyen

Read further on "current gain" or Hfe, alpha, or Beta for transistors. The transistor you choose will affect the level of current gain for your calculation. Another thing to read up on is "saturation" where you can start to understand how much base overdrive gives you what saturation voltage, information also found in the transistor data sheet.

Reply to
John_H

I also had trouble reading the schematic. Here is my solution:

Use a pnp bipolar transistor, any one will do. Connect the emitter to the FPGA/CPLD output. Connect the collector through 200 Ohm to the negative voltage (-1.3 V) Connect the base through a 1000 Ohm resistor to ground.

This structure is non-inverting and does not amplify the current. The output rise time is very fast, the fall time depends on the capacitive load. e.g. 200 Ohm x 20 pF = 4 ns

Peter Alfke, Xilinx Applications

Reply to
Peter Alfke

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