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How to snoop an inout signal in EDK?

For example, signal A is an inout signal of certain IP and connected to an external pin of the FPGA with a net(let's call it net_A). What I want to do is to add another pin just for output, and connect net_A to it. When I did this in EDK, I always got an MDT error message:

ERROR:MDT - ....connector is connected to both uni and bi-directional ports!

  1. What should I do if I want to connect net_A to the two ports? Maybe FPGA_editor can do this work, what about EDK?
  2. Can the error above be supressed by certain configuration to EDK?
Reply to
Perry
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A somewhat easy workaround is to use the Xilinx provided util_vector_logic core. It one of the IP available in the utility section of the EDK cores. I have two in my project right now just so i can route some things up to the top without having to buffer them in the custom IP.

I just use an AND funtion and tie one of the input high and the other to my signal of interest. Then the output gets routed out externally. You'll have to rebuild, but that shouldn't be a big deal.

Reply to
motty

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