Execute from SPI flash

More info: Advance data is here

Still an 8 pin package (or SO16 where die is too large )

Best speed is from Fast Read Quad I/O opcode

Looks like the first byte is 1-bit SPI (8Ck), then the 32 bit address is loaded 4 bits wide (8Ck), then 4 wait clocks, and then bytes stream out two Ck per byte, so the latency to first byte is 8+8+4+2 = 20-22clks, and the Speed-Equivalent-Skip is 10 bytes - ie for short forward jumps, of up to 10 bytes, you are better to simply skip, than re-address. Clock is 80MHz, gives 320MBd, or 40 MBytes/s memory bandwith. Enough for some serious uC programming, and you can split into 2 SPI devices, and double that again, or perhaps x3, for 18-24 bit opcode cores ?

-jg

At what point do you call it a parallel flash (admittedly with an address counter built in :-)

Cheers, Martin

You are right :) - they are inching [nibbling ? ;) ] their way back to the memory segment that has mostly died off (except in some game cartridges ?) of Address latched and Clocked Code Flash/Rom Memory.

Still, getting a Nibble-wide memory in a 8 pin package is quite nice, and using 2-3-4 of these is probably quite practical.

From an energy and EMC angle, it makes much more sense to have a loadable address counter, so I hope these contine to expand. Next, we might see Byte-wide ones in SO16 ?

-jg