Virtex5 LXT Clock Distribution

I am using four GTP transceivers of V5 LXT 110T FPGA. I used coregen to create the verilog output.

When I looked at the verilog output, the 200MHz reference clock was fed to the GTP tile from the differential clock input reference pins. The clock connection looks like this:

Input pin to Tile0 Input clock pin

Tile0 output to Bufg input

Bufg output to PLL input.

Pll generates two outputs:

(1) One clock is fed back to the tile (2) Second clock is used by the FPGA fabric to feed the data to the transceivers

My questions are:

(1) Why PLL is needed in this and is fed back to the Tile. The PLL is not really multiplying or dividing the clock in this case. Virtex 5 has very limited PLL resources. I would like to avoid using PLL for this. Is there an alternative?

(2) why the second clock output from the PLL which used by the FPGA farbic is not assigned a bufg? The coregen uses this to clock out the data from BRAM but in a real application, it may have more loads. Why BUFG is not used here but is used to feed only one clock from the tile to the PLL?


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Eddie H
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