I would like to ask some questions regarding a Xilinx JTAG programmer:
First, it seems that the programmer doesn't actually connect to the LPT port because of gender mismatch. Luckily I have a parallel port gender changer. Is this still ok?
Second point, I connect the programmer and start up xilinx ise and impact. I get a message that many unknown devices are being detected, is this normal?
Last point, the download cable seems to be some sort of 2 x 8 block socket, i.e. 16 pins, how do I identify the required pins i.e. vdd,gnd,tdi,tms,tck,tdo?
Thanks in advance