Field-Programmable Gate Arrays

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kicad or orcad virtex5 symbol

Hi all, I'm designing a board based on a virtex5 (XC5VLX50). I'm surprised, I can't find virtex 5 symbols for using wit...
4 comments posted 19yrs
posted by michel.talon
4 comments posted 19yrs posted by michel.talon

code coverage in modelsim_se

how to merge multiple missed coverage files to see final uncoverd lines in one file? thanks in advance.
0 comments posted 19yrs
posted by kalvarajesh2003
0 comments posted 19yrs posted by kalvarajesh2003

Free Background Check

I ran across this site and its pretty neat. You can sign up for free and conduct your own background check. Free Backgro...
0 comments posted 19yrs
posted by sn666h9dsoou8jqmp65q
0 comments posted 19yrs posted by sn666h9dsoou8jqmp65q

JTAG interconnect testing, prototypes

Hi, I am looking at various alternatives for interconnect testing, especially for prototype boards that have BGAs. I am...
9 comments posted 19yrs
posted by tony
9 comments posted 19yrs posted by tony

FiberChannel SOF

Would some one know why SOF/EOF of Fiber Channel frame is 4 bytes? Thanks Walters
2 comments posted 19yrs
posted by hpsham
2 comments posted 19yrs posted by hpsham

Opteron performance tuning (for Quartus / Linux)?

Thanks in advance for the help! ---------------------------------------- My employer just acquired a SunFire server w 1...
5 comments posted 19yrs
posted by jjohnson
5 comments posted 19yrs posted by jjohnson

Virtex 13?

I was just eating some spicy food for lunch and I started wondering whether Xilinx would eventually come out with a Virt...
4 comments posted 19yrs
posted by nimby_NEEDSPAM
4 comments posted 19yrs posted by nimby_NEEDSPAM

Daisy chaining FPGA with CPLDs

I'm not even sure if this might be a stupid question. I have a Xilinx app note on daisy-chaining FPGA configurations, bu...
4 comments posted 19yrs
posted by pomerado
4 comments posted 19yrs posted by pomerado

Problem about ADV7181B debugging

Hi, Everyone. I am debugging an image capture board. In this board, th ADV7181B is used to digitalize one channel analo...
0 comments posted 19yrs
posted by dechenxu
0 comments posted 19yrs posted by dechenxu

Best way to export XPS project to ISE?

I have a design that was built with XPS 8.2.03. I want to lock down everything in the design except one custom OPB peri...
1 comments posted 19yrs
posted by cepope
1 comments posted 19yrs posted by cepope

xup-v2p: Only USB 1.1

Hello, I'm working with a new xup rev. 04 board: Whenever I connect the integrated USB Platform cable I only get USB fu...
1 comments posted 19yrs
posted by joerg
1 comments posted 19yrs posted by joerg

JPEG-LS hardware implementation

Hi All, We are an enthusiasts who are written hardware JPEG-LS IP core. Visit project site http://www.jpegls.com. It's...
8 comments posted 19yrs
posted by Michael.Tsvetkov
8 comments posted 19yrs posted by Michael.Tsvetkov

Optimized bitcounting on FPGA

Hi, I am currently working on a circuit which has to perform Hamming distance computation between large bit vectors (>5...
7 comments posted 19yrs
posted by sderrienREMOVE
7 comments posted 19yrs posted by sderrienREMOVE

FFT core

[posted to comp.arch.fpga + comp.lang.vhdl] Hi All I've had a quote from a 3rd party to develop a floating point FFT co...
11 comments posted 19yrs
posted by grumpsnothere
11 comments posted 19yrs posted by grumpsnothere