Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Companies that Manufacture Multi-FPGA Hardware
Hi, I am a Grad student. I intend to do a project examining the aspects surrounding interconnections between FPGAs. I figure that this group might have professionals working in this area - so it would...
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16 years ago
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XUPV2P serial connection through serial-to-usb cable
Hi, I'm trying to test the golden PROM configuration on my XUP Virtex II Pro board. Trouble is that I'm not able to use the serial interface to carry out Built-In Self Tests. I'm using a serial-to-usb...
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16 years ago
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Detecting if an error happened in ModelSim
Is there a way to detect if an error or warning occured during a simulation run in ModelSim scripting. I'm just trying something simple: what I'd like to do is have my test bench simulation set up...
8
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16 years ago
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Tcl - Xilinx - ISE - WindowsXP
Hello, I started to learn tcl for support my design work. I try to use Xilinx' tools without GUI. I can't find method to config "Generate Programming File" bitgen tool in tcl shell. One way I find is...
4
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16 years ago
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Partial/Incorrect configuration of FPGA from flash PROM.
Dear All Summary: FPGA performs properly when configured by a BIT file but one function is performing incorrect when it is configured from the flash PROM, programmed with an MCS file generated from...
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16 years ago
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Basic VHDL Development kit
Does anybody have any suggestions for a cheap and basic development kit to practice VHDL on? It doesn't need to do much more than toggle a few output pins and I'm happy to make up my own programming...
21
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16 years ago
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Any better ways for interfacing fpga with dynamic memory?
Hi, I tried to interface a dynamic memory controller (dmc) inside an fpga with a sdram on the fpga board. The problem was that the dmc is 32bits wide (due to pin constraints) but the sdram is 64bits...
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16 years ago
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CFP: SCALABLE COMPUTING. Special Issue on High Performance Reconfigurable Computing (HPRC)
Special Issue of Journal of Scalable Computing: Practice and Experience High Performance Reconfigurable Computing (HPRC) High Performance Reconfigurable Computing (HPRC) has become a crucial research...
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16 years ago
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Virtex4: ISERDES -> FIFO -> BlockRAM fails
Hi all, We are trying to do the same as in XAPP 704 in the simple examples. All on a Xilinx Virtex4 SX. We have LVDS inputs, ISERDES, a FIFO, which is all fine. As soon as we try to connect the output...
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16 years ago
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ALTERA Quartus 7.2 under MS Vista
Have you tried it yet? How do you like it? Does it solve the horrible slow opening of Nios II components in SOPC Builder?
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16 years ago
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Test and Measurements - Large FPGA
Hi, Is there any body uses the Large FPGA to build test and measurements equipments. If you use it, how big is the idle FPGA for you. thanks Narsi
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16 years ago
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Spartan3E DDR clock feedback
Hi all, I am designing a Spartan3E board with a DDR SDRAM. The DDR is, similarly as in Spartan3E Starter Kit but connected to bank1 (2.5V with 1.25V reference) for lower routing delay. The Spartan3E...
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16 years ago
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Count Leading Zero (CLZ) possible by MicroBlaze??
Hi all, does anyone know if the MicroBlaze Processor of Xilinx has the CLZ Instruction? I took a look in the datasheet, but didn't find anything about it. I would like to count the number of zeros in...
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16 years ago
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Error in simple code, plz help
Hello, I'm beginner in VHDL and practice with Xilinx ISE 9.2. I want to test and with generic, the code is similiar to "Circuit Design with VHDL" books cod and I don't understand where is problem. The...
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16 years ago
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Xilinx ISE 'feature': forcing a DUT signal
Has anyone managed to get a Verilog testbench to force an internal DUT signal using ISE (9.2i)? This seems to be impossible. A DUT force has to be, pretty much by definition, hierarchical. If you try...
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16 years ago
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