Hello, I'm beginner in VHDL and practice with Xilinx ISE 9.2. I want to test and with generic, the code is similiar to "Circuit Design with VHDL" books cod and I don't understand where is problem. The synthesiser shows error: "Lin
- parse error, unexpected RANGE"
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gener_test is generic(n: integer := 8); port (input: in std_logic_vector(n-1 downto 0); output: out std_logic); end gener_test;
architecture Behavioral of gener_test is signal tmp1: std_logic_vector(n-2 downto 0);
--signal tmp2: std_logic; begin process(input) begin tmp1(0)