Field-Programmable Gate Arrays

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HELP, how to time constraint part of a design?

Hello Could someone tell me how to make timing constraints in a particular part of a VHDL design? Inside my design I ha...
13 comments posted 19yrs
posted by DoVHDL
13 comments posted 19yrs posted by DoVHDL

What happened to Confluence and HDCaml?

It seems that the launchbird site has disappeared. I had heard that Confluence was superceded by HDCaml, but it looks l...
4 comments posted 19yrs
posted by rubyfan
4 comments posted 19yrs posted by rubyfan

Compiler Options

Hella all:) I would like to ask for the complier option in the XILINX EDK. I have written ans inline assembly code. and...
2 comments posted 19yrs
posted by lastval
2 comments posted 19yrs posted by lastval

Unrouted nets (Xilinx FPGA Editor)

Hi all, I meet some problems in the P&R process of my design. The Place & Route Report shows the following messages. Be...
2 comments posted 19yrs
posted by eejju
2 comments posted 19yrs posted by eejju

Xcell Article on 1.2Gsamples/sec FFT

Hi all, Just read an interesting article in Xilinx's xcel publication. Lots of technical detail, and no "marketing" to...
3 comments posted 19yrs
posted by andrew.newsgroup
3 comments posted 19yrs posted by andrew.newsgroup

Timing Constraint Question

I am working with an EDK design that utilizes an MPMC2 core. There are several clocks associated with this core. All of...
1 comments posted 19yrs
posted by mottoblatto
1 comments posted 19yrs posted by mottoblatto

Legacy support of a Max 7000S

Group, I have the need to copy a Max 7000s device that was originally developed under Max+Plus II. I am not able to loc...
2 comments posted 19yrs
posted by Noway2
2 comments posted 19yrs posted by Noway2

DDR DIMM clock distribution

Hi I'm using Cyclone II EP2C8 in PQFP208 package and DDR DIMM. And I'm wondering how to distribute clock signal. DIMM h...
1 comments posted 19yrs
posted by "SwietyMikolaj["
1 comments posted 19yrs posted by "SwietyMikolaj["

8B/10B Xilinx Paper

Hello newsgroup, I am trying to understand the Xilinx reference design (XAPP391: Design of a 16b/20b Encoder/Decoder Us...
3 comments posted 19yrs
posted by ALuPin
3 comments posted 19yrs posted by ALuPin

code coverage in modesim se 6.1f

hi , how can i save the coverage data , so that the output file contains the missed coverage lines and/or coverage line...
0 comments posted 19yrs
posted by kalvarajesh2003
0 comments posted 19yrs posted by kalvarajesh2003

CY22393

I need info about programm FLASH without external programmer.When I program this IC from I2C I rpogramm volatile configu...
1 comments posted 19yrs
posted by axalay
1 comments posted 19yrs posted by axalay

Need suggestion on FPGA kit

Hi friends I am working in a pvt concern.We are decided to purchase FPGA trainer kit. But we are confused with Xilinx-V...
9 comments posted 19yrs
posted by thiyagu.in
9 comments posted 19yrs posted by thiyagu.in

Neural Coprocessor with Xilinx EDK

Hi, I'm a Computer Science student and for my final year project I have chosen to implement a Neural Network Co-process...
0 comments posted 19yrs
posted by obviouslyadummy
0 comments posted 19yrs posted by obviouslyadummy

Cyclone II - PLL differential output

Hi I have read on this group that it is required 4 pads space from LVDS differential signals to single-ended pin. Is thi...
2 comments posted 19yrs
posted by "SwietyMikolaj["
2 comments posted 19yrs posted by "SwietyMikolaj["