Partial/Incorrect configuration of FPGA from flash PROM.

Dear All

Summary: FPGA performs properly when configured by a BIT file but one function is performing incorrect when it is configured from the flash PROM, programmed with an MCS file generated from the good BIT file.

Detailed: I am using a SPARTAN 3 (XC3S505PQ208C) with a (XCF02SVO20C) flash PROM in the ISE 7.1i environment. The circuit and my VHDL code was working properly until recently. I am sure nothing major changed but I am experiencing a problem which I cannot solve.

I read 4 registers from the FPGA via an ISA bus interface into a PC. Three of these registers are hard coded and in the fourth register a bit is populated by a watchdog function implemented on the FPGA. The watchdog is serviced by writing to a register in the FPGA at a certain rate. When the watchdog is not timed out this bit is set to zero otherwise it is one

I generate the BIT file for the FPGA and from it the MCS file for the PROM. After programming the PROM and cycling the power to configure the FPGA from the PROM the 3 hard coded register are read correctly but the watchdog bit in the fourth register indicates a watchdog time out (i.e. logic 1) even though the watchdog is reset and serviced properly. I assume that the configuration process is done properly since iMPACT indicates no problems except for the usual (WARNING:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the bitstream stored in memory, but the original bit stream file remains unchanged) which I have seen since the first time I started using ISE. The other functions implemented on the FPGA works properly. This includes switching relays by writing to registers in the FPGA etc. I have changed between CCLK and JTAG Clock in [Generate Programming File >> Startup Options tab] with no success. I have also replaced the flash PROM.

Without changing anything I configure the FPGA with the BIT file and the everything works properly. After reseting the watchdog timer and servicing it properly the bit in the register is read as 0 indicating that the watchdog happy. The other registers are read properly as in the case where the FPGA is configured from the PROM.

What could be the problem? Partial configuration/ Wrong settings? What can i do to get rid of the warning messages mentioned above?

Partial configuration is unlikely. I would suggest looking at start-up issues. Does your design have some sort of global reset you can apply after configuration? Perhaps you could use this to see if the two configuration methods show similar results.

Another possibility is the state of the surrounding circuitry at the time of configuration. Since you power cycle the FPGA when loading from PROM it's possible that some external logic is not in the same state as when you use IMPACT. Are you using the PlatformFlash serial flash for your system? If so you can try checking the "Load FPGA" button when you program the flash from iMPACT. This would still load the FPGA from the flash, but without power-cycling the system so you can see if this is a system start-up issue.

HTH, Gabor