Has anyone managed to get a Verilog testbench to force an internal DUT signal using ISE (9.2i)? This seems to be impossible.
A DUT force has to be, pretty much by definition, hierarchical. If you try something like
force top.mod.x = y; // or... assign top.mod.x = y;
you get a message about an unsupported hierachical expression. Tweaking the assignments eventually gives you the catch-all unsupported constructs message, with details in #24068 and an accompanying pdf doc. The suggested work-around - to add new ports to the DUT - isn't helpful.
The ISE docs claim to support 'procedural continuous assignments', but this seems to be a rather wide definition of 'supported'.
Thanks -
Evan