Field-Programmable Gate Arrays

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Detecting if an error happened in ModelSim

Is there a way to detect if an error or warning occured during a simulation run in ModelSim scripting. I'm just trying...
8 comments posted 18yrs
posted by kmaryan
8 comments posted 18yrs posted by kmaryan

Tcl - Xilinx - ISE - WindowsXP

Hello, I started to learn tcl for support my design work. I try to use Xilinx' tools without GUI. I can't find method t...
4 comments posted 18yrs
posted by jerzy.gbur
4 comments posted 18yrs posted by jerzy.gbur

Basic VHDL Development kit

Does anybody have any suggestions for a cheap and basic development kit to practice VHDL on? It doesn't need to do much...
21 comments posted 18yrs
posted by news
21 comments posted 18yrs posted by news

Virtex4: ISERDES -> FIFO -> BlockRAM fails

Hi all, We are trying to do the same as in XAPP 704 in the simple examples. All on a Xilinx Virtex4 SX. We have LVDS in...
0 comments posted 18yrs
posted by jobeck
0 comments posted 18yrs posted by jobeck

ALTERA Quartus 7.2 under MS Vista

Have you tried it yet? How do you like it? Does it solve the horrible slow opening of Nios II components in SOPC Builder...
1 comments posted 18yrs
posted by Pszemol
1 comments posted 18yrs posted by Pszemol

Test and Measurements - Large FPGA

Hi, Is there any body uses the Large FPGA to build test and measurements equipments. If you use it, how big is the idle...
6 comments posted 18yrs
posted by pnarsi
6 comments posted 18yrs posted by pnarsi

Spartan3E DDR clock feedback

Hi all, I am designing a Spartan3E board with a DDR SDRAM. The DDR is, similarly as in Spartan3E Starter Kit but connec...
0 comments posted 18yrs
posted by ales.gorkic
0 comments posted 18yrs posted by ales.gorkic

Count Leading Zero (CLZ) possible by MicroBlaze??

Hi all, does anyone know if the MicroBlaze Processor of Xilinx has the CLZ Instruction? I took a look in the datasheet,...
6 comments posted 18yrs
posted by armandolou
6 comments posted 18yrs posted by armandolou

Error in simple code, plz help

Hello, I'm beginner in VHDL and practice with Xilinx ISE 9.2. I want to test and with generic, the code is similiar to...
2 comments posted 18yrs
posted by VladimirMatvejev
2 comments posted 18yrs posted by VladimirMatvejev

Xilinx ISE 'feature': forcing a DUT signal

Has anyone managed to get a Verilog testbench to force an internal DUT signal using ISE (9.2i)? This seems to be imposs...
3 comments posted 18yrs
posted by nospam
3 comments posted 18yrs posted by nospam

Synplicity and the Xilinx MAP Memory Monster

I have a design which uses around 80% of an XC5V330. Synthesis to EDIF is via Synplicity and it's pretty quick. MAP is...
2 comments posted 18yrs
posted by tim
2 comments posted 18yrs posted by tim