Latest threads in Field-Programmable Gate Arrays

Companies that Manufacture Multi-FPGA Hardware

Hi, I am a Grad student. I intend to do a project examining the aspects surrounding interconnections between FPGAs. I f...

7 19yrs

olson_ord

7 19yrs olson_ord

XUPV2P serial connection through serial-to-usb cable

Hi, I'm trying to test the golden PROM configuration on my XUP Virtex II Pro board. Trouble is that I'm not able to use...

1 19yrs

rhishi

1 19yrs rhishi

Detecting if an error happened in ModelSim

Is there a way to detect if an error or warning occured during a simulation run in ModelSim scripting. I'm just trying...

8 19yrs

kmaryan

8 19yrs kmaryan

Tcl - Xilinx - ISE - WindowsXP

Hello, I started to learn tcl for support my design work. I try to use Xilinx' tools without GUI. I can't find method t...

4 19yrs

jerzy.gbur

4 19yrs jerzy.gbur

Partial/Incorrect configuration of FPGA from flash PROM.

Dear All Summary: FPGA performs properly when configured by a BIT file but one function is performing incorrect when it...

1 19yrs

christovt

1 19yrs christovt

Basic VHDL Development kit

Does anybody have any suggestions for a cheap and basic development kit to practice VHDL on? It doesn't need to do much...

21 19yrs

news

21 19yrs news

Any better ways for interfacing fpga with dynamic memory?

Hi, I tried to interface a dynamic memory controller (dmc) inside an fpga with a sdram on the fpga board. The problem w...

0 19yrs

camwwang

0 19yrs camwwang

CFP: SCALABLE COMPUTING. Special Issue on High Performance Reconfigurable Computing (HPRC)

Special Issue of Journal of Scalable Computing: Practice and Experience High Performance Reconfigurable Computing (HPRC...

2 19yrs

eferrer000

2 19yrs eferrer000

Virtex4: ISERDES -> FIFO -> BlockRAM fails

Hi all, We are trying to do the same as in XAPP 704 in the simple examples. All on a Xilinx Virtex4 SX. We have LVDS in...

0 19yrs

jobeck

0 19yrs jobeck

ALTERA Quartus 7.2 under MS Vista

Have you tried it yet? How do you like it? Does it solve the horrible slow opening of Nios II components in SOPC Builder...

1 19yrs

Pszemol

1 19yrs Pszemol

Test and Measurements - Large FPGA

Hi, Is there any body uses the Large FPGA to build test and measurements equipments. If you use it, how big is the idle...

6 19yrs

pnarsi

6 19yrs pnarsi

Spartan3E DDR clock feedback

Hi all, I am designing a Spartan3E board with a DDR SDRAM. The DDR is, similarly as in Spartan3E Starter Kit but connec...

0 19yrs

ales.gorkic

0 19yrs ales.gorkic

Count Leading Zero (CLZ) possible by MicroBlaze??

Hi all, does anyone know if the MicroBlaze Processor of Xilinx has the CLZ Instruction? I took a look in the datasheet,...

6 19yrs

armandolou

6 19yrs armandolou

Error in simple code, plz help

Hello, I'm beginner in VHDL and practice with Xilinx ISE 9.2. I want to test and with generic, the code is similiar to...

2 19yrs

VladimirMatvejev

2 19yrs VladimirMatvejev

Xilinx ISE 'feature': forcing a DUT signal

Has anyone managed to get a Verilog testbench to force an internal DUT signal using ISE (9.2i)? This seems to be imposs...

3 19yrs

nospam

3 19yrs nospam

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