Any better ways for interfacing fpga with dynamic memory?


I tried to interface a dynamic memory controller (dmc) inside an fpga with a sdram on the fpga board. The problem was that the dmc is 32bits wide (due to pin constraints) but the sdram is 64bits wide. So, to interface the 32 bits wide dmc with the 64 bits wide sdram, I have to use the cpu r/w address bit[2] to differentiate between lower half and higher half of the 64 bits interface. Just wondering whether there are better methods that I can use to interface 32 bits dmc with 64bits dram. thanks!

btw, the translation mechanism between normal address and dram row/col addresses would be useful.

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Wei Wang
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