Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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create JAM-File for Xilinx device
Hi there i'm currently trying to configure Alteras JAM Player for a Mitsubishi M16 Controller to program multi vendor device JTAG chains. Input files are either *.jam (JAM file) or *.jbc (JAM-ByteCode...
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20 years ago
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RE:can you please post a summary of your findings to the group?
-----Original Message----- From: Arrigo Benedetti [mailto: Sent: 02 July 2003 15:06 To: Aziz AhmedSaid Subject: Re: Does anyone know about hardware implementations of the SVD ? Hi Aziz, can you please...
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20 years ago
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[DLL Virtex/Spartan-II] Which is the right feedback in x1 and x2 Appl
Hi All, I discovered that I use in my working application the x2 Clock Output as the feedback - after the GBUF - for a DLL that deskews a 48Mhz input clocks and provides to output clocks for internal...
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20 years ago
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check one two check check
check check one twoo
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20 years ago
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What a fascinating board!
Who makes the best FPGA? Lattice or Cypress?
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20 years ago
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ARM+FPGA
Hello, I am looking for an ARM (preferably StrongARM) w/ FPGA development board. StrongARM preference is for mainly for Linux. Any other supported processor will do as well. Thanks a lot! -Sumeet
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20 years ago
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post-PAR simulation model
in ISE project navigator, when I run the 'generate post-PAR simulation model' process, I get a warning below: WARNING:NetListWriters:108 - In order to compile this verilog file successfully, please...
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20 years ago
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XPLA3 vs. MAX3000A
I know this is an FPGA news group, and my question is about CPLDs, but there did not seem to be a CPLD news group! So here goes... I am comparing these two families. Going to pick one of the two for a...
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20 years ago
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Re: VHDL & OV6620 CMOS camera
"PC" wrote in message news:3f033fb1$0$4611$ ahem, no, it's just that (I quote the website) (NDA = Non Disclosure Agreement, a confidentiality contract agreeing that you won't give away any technical...
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20 years ago
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New FPGA RISC C-NIT
Visit the website for C-NIT at Sumit
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20 years ago
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NIOS tutorial for the Stratix1S10
I'm trying to follow the NIOS tutorial for the Stratix1S10. At one point, page 16 of the 'tt_nios_hw_stratix_1s10.pdf' I should start the SOPC builder. A quick console window opens, to fast to...
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20 years ago
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Virtex 2Pro, ML300, VP2PDK, EDK, etc..
Hi just a few comments, hope the may save some time for someone ML300 is shipped with V2PDK most V2Pro 'reference designs' are only for V2PDK V2PDK is no longer supported by xilinx the V2PDK examples...
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20 years ago
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Process variable setup times and propogations
Reposting: Sorry for the earlier mess. The Xilinx newsgroup portal apparently chewed my origional posting! Greetings folks, I am having a strange time with some code I recently wrote to implement a...
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20 years ago
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Re: PCB Problem
What's the voltage on your supply rails/planes on the side that you expect to be off? My guess is that you have some signals going from the expect-to-be-on section to the expect-to-be-off section, and...
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20 years ago
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Re: How to get 27MHz from 10 MHz in FPGA???
Yes you could "pre-multiply", but that involvs extra circuitry. And a doubler generates frequency modulation, if it is done by differentiation both incoming edges. It's much nicer to be able to forget...
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20 years ago
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