Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Discrepancy in CLB Usage Report
Hi, I am using the following flow: VHDL - Entry Synplify Pro - Synthesis Xilinx Design Manager - Post synthesis, place and route, etc. The target device is Xilinx Spartan XL - XCS20XL. I am trying to...
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20 years ago
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Re: ASIC divider in FPGA?
an FPGA. bound to small. Algorithms like that used in the IBM 360/91 or Cray-1 could be implemented as combinatorial dividers. An iterative algorithm like the 360/91, or fully pipelined like the...
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20 years ago
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Re: Everything need a reset?
'0' There are designs that in reality don't need a reset, but do in simulation. Others need a reset in both cases. -- glen
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20 years ago
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Re: Does anyone know about hardware implementaions of the SVD ?
Doing floating point in an FPGA is pretty expensive (in terms of CLBs used). I do wonder how big your array is? -- glen
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20 years ago
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Re: defparam LUT_4
reposting in plain text Kris, The value E4E4 is the hex value in the LUT that is derived from a truth table: inputs | output 4 3 2 1 | out ------------- 0 0 0 0 | 0 0 0 0 1 | 0 0 0 1 0 | 1 0 0 1 1 | 0...
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20 years ago
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Combining Distributed RAM and Block RAM
Hi, I need to use a memory with 37bits width. If I take a Block RAM Primitive RAMB16_S36_S36, 36 bits can be utilised for storage (32bits data + 4bits parity) But I don't want to instantiate another...
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20 years ago
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Xilinx Methodology Questions : Unconstrained Paths and DLL output phase alignment.
Hi I have two questions regarding Xilinx designs. [1] How do I identify which paths the static timing analyzer considers to be unconstrained? This has been an ongoing, frustrating task for me. I am an...
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20 years ago
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Looking for DIMM format FPGA board
I'm looking for a DIMM format FPGA board like Pilchard or the AcB from (now defunct?) Nuron. I've done several web searches, but found nothing that both fits the bill, and is from a company that is...
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20 years ago
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Fixed point signed multiplication algorithm
Hello, I am implementating Fixed point signed multiplication. Is there a algorithm to implement it. I have done the usual method of multiplication i.e partial products ...shift and add method. But its...
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20 years ago
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Re: projects for beginners
Have a look at -- we have several free PLD tutorials there including info on Xilinx, Altera, Verilog, etc. Al Williams AWC
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20 years ago
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Re: 48bit adder won't fit
Without more description it would be hard to say. If the whole design could be implemented serially it would make a lot of sense. If a parallel 48 bit output is needed, then deserializing the result...
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20 years ago
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Why not DDR in FPGAs?
Hi all, here is a quit simple, general question: Why do the FPGAs (as fare as I know) not use Double Data Rate on Chip for their FlipFlips? + This would reduce the power for the clock tree. + I could...
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20 years ago
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Re: MapLib:93 - Illegal LOC on symbol "clk.PAD" (pad signal=clk) or BUFGP symbol "u1" (output signal=u1), IPAD-IBUFG should only be LOC'd to GCLKIOB site."
Hello, The synthesis tool is identifying your signal as clock and instantiating a clock buffer. This has to be loc'ed to a gclkiob. If you do not want the synthesiser to instantiate clock buffer, in...
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20 years ago
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Regarding NRZ
Hi everyone, Iam basic to the communication design, I have a query regarding NRZ interface with FPGA, Can we provide NRZ interface to FPGA, how does the voltage level will be at the interface ? Is it...
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20 years ago
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FPGA Editor and Xilinx ISE 5.1i
Hi all! I'm trying to make a hard macro of a design and I got that error: FATAL_ERROR:Ncd:basncmacrodef.c:1466:1.19.2.1 - Mangled nmc file start property read Seems like the FPGA Editor tool has...
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20 years ago
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