Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Re: Excel and FPGA's
Hi - Well, maybe. But I've felt for years that my chances of getting a design to work are inversely proportional to the number of tools between me and the target device. Bob Perlman Cambrian Design...
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hidden remap failed
when trying to do a simulation, I get this: Completed process "Generate Post-Translate Simulation Model". ERROR: Hidden remap failed Reason: Launching Application for process "Simulate Post-Translate...
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division
hello there i am relatively new to VHDL..this might sound simple any ideas how to carry out division (floating point) in VHDL??
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Re: Starter Question and Opinion on VHDL
A follow up: Someone sent this solution to me and said it would provide no assymetrical delays and would be better than a long elsif chain. Does anyone else have any experience with this? It seems to...
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information required
Hi everyone,        Iam an student having doubt in LVDS communication, Let say xilinx vertex FPGA is used for this pupose.        I have LVDS transmitter and receiver, No AC coupling is...
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DCM usage question
such a application 40MHz clkin, 20MHz clkdv output and 30MHz clkfx output use clk0 feedback to clkfb can both the clkdv and clkfx's de-skew be guaranteed?
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constraints, etc
Hello all, I would like to know a couple of things if anyone could help or point me to a file etc. I'm using Webpack from Xilinx, and a Spartan XC2S100 and I've been messing around with writing simple...
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okay what am I missing??? Please
Could someone please let me in on how the Flip Flops work in ISE Webpack schematics. Where is the Q/ . Do I simply run an inverter off from Q or what. Are these also global clk and rst or only if you...
 
Difficulty with OPB bus and user IP
Using the Memec MB1000 eval board with the Virtex-2 on it, I tried one of the Memec projects "Lab06_Own_Periph_VirtexII1000". Building this under the EDK 3.2 works fine on eval board. But, if I change...
 
Quartus II 3.0 Release & Web Edition Download Links
Quartus II software version 3.0 is now available on the PC, Solaris, Red Hat Linux, and HP-UX operating systems. Customer CD shipments will be made from July 11 - July 21. The Web Edition is available...
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Questions about Design Compiler.
Hi, I'm new to Synopsys Design Compiler. I have some questions: 1. Should I always set drive strength and load driven by the ports before optmization? But I don't know what kind of value i can use and...
 
ACEX (EP1K) Power-Up Current
Since Altera seems to be active in this group, I will ask the question here. I have finally gotten an acceptable price on the EP1K30 part (5 volt tolerant) and will be using it in my design provided I...
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Re: xilinx and web pack questions newbe
Version 5.2 only works on windows 2000. I am using 3.2 as it seems to be the only one that works on my setup. I have also assigned the input and outputs to pins using the user constraints, but I did...
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Re: Parallel processing
"Gian" asked "Is it possible to simulate a VLIW multiprocessor using a FPGA devise ?" You may find useful the postings at FPGA CPU News on and around this topic: Jan Gray, Gray Research LLC
 
Re: cyclone on pci?
Altera will be shipping a Cyclone, 1C20-based PCI development kit soon. Introduction is slated for late August. Cost will be under $1000, and it will include DDR ram and be in a short board form...
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