XPLA3 vs. MAX3000A

I know this is an FPGA news group, and my question is about CPLDs, but there did not seem to be a CPLD news group! So here goes...

I am comparing these two families. Going to pick one of the two for a bunch of new designs. After comparing the features, the XPLA3 seem to be much better bang for the buck compared to the MAX3000. Price seems to be equal, but on a feature basis the XPLA3 is significantly better.

However, Xilinx cut the XPLA1 and XPLA2 lines. My fear is that the same could happen to XPLA3. The Altera folks tell me that Altera/MAX has huge market share and focus in CPLDs, while CPLDs only account for 10% of Xilinx business.

Any comments? Do you think the XPLA3 parts are gonna stay in production over the long haul?

Thanks, Chris.

Reply to
chris_s
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I'd also look at the Atmel ATF15xx, and Lattice ispMAX4000 families. Altera may have the largest CPLD chunk, but they have not done much in an Architectural sense, and their Icc is quite high.

Xilinx have the newer XC2 in front of the XPLA3, so you could spin a design, and check the FIT in both families.

With Atmel, Lattice and Xilinx all offering low static Icc CPLDs, Altera are looking a tad dated.

-jg

Reply to
Jim Granville

So both of you are suggesting going a different direction than Altera.

I have been burned twice before by prog logic parts going away. That's why I am only going to consider designing in something that is in widespread use - either Altera or Xilinix. Its got to be around for >10 years.

The Xilinx XPLA3 are better parts than the MAX3000. Even the Altera FAE here admits it. But are they going to be around in the future? I know MAX3000 will be around because there are tons of people using them. I just don't know how many XPLA3 are in use.

Won't touch Atmel, Lattice or anything else. Too risky, too little market share.

My requirement is full 3.3V in and out. So XC2 is no good (2.5V).

The Altera people told me that a new CPLD family is coming out soon. It will be lower power. Sounds like Altera has gotten very sick of hearing their parts are current hogs.

Xilinx says that they also have a new CR (2.5V) part coming out, but it will probably replace the XC2 line, not XPLA3. They say XPLA3 is not going to be obsolete.

Does not sound like either of you are using the XPLA3. That concerns me.

Chris.

Reply to
Chris_S

Chris_S wrote: : So both of you are suggesting going a different direction than Altera.

: I have been burned twice before by prog logic parts going away. That's why : I am only going to consider designing in something that is in widespread : use - either Altera or Xilinix. Its got to be around for >10 years.

: The Xilinx XPLA3 are better parts than the MAX3000. Even the Altera FAE : here admits it. But are they going to be around in the future? I know : MAX3000 will be around because there are tons of people using them. I just : don't know how many XPLA3 are in use.

: Won't touch Atmel, Lattice or anything else. Too risky, too little market : share.

: My requirement is full 3.3V in and out. So XC2 is no good (2.5V).

...

XC2 (Coolrunner II) is 3.3 Volt in and out, if you provide that IO voltage.

Bye

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply to
Uwe Bonnes

Hi gang - sorry for the marketing blitz below :)

Hi Chris - Lattice has over 40% marketshare in CPLD, ALtera has over 40% market share in CPLD, Xilinx is ~10% in CPLD. Lattice has obsoleted very few of the CPLD device families introduced over the past 11 years ( some older MACH devices from the Vantis acquisition, mainly). Lattice offers multiple different architectures in CPLD, from 32 macrocells to 1024 macrocells, in 1.8v, 2.5v ,3.3v, and 5v. I would strongly recommend Lattice at least be given a close look.(of course I am a bit biased :) ) I am not sure where "nospam.com" is located, but I am willing to bet we have resources neardby! A local FAE would be happy to talk with you.

Our downloadable LEVER3 starter software includes Synplicity for VHDL/VERILOG synthesis, ABEL and Schematic capture, funtcional and timing simulation. Supports all product families.

Michael Thomas LSC SFAE New York/New Jersey

631-874-4968 fax 631-874-4977 snipped-for-privacy@latticesemi.com for the latest info on Lattice products -
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Reply to
Mikeandmax

Chris_S wrote: :> XC2 (Coolrunner II) is 3.3 Volt in and out, if you provide that IO : voltage.

: Yeh I guess you are right, but not with a single supply of course. I would : have to add regulators everywhere for the 1.8V cores and that might become a : pain.

A small SOT23 regulator fits nicely below the Coolrunner (Coolrunner on top, regulator on botton). So no need for an extra supply layer. XC2C is not sensitive to power sequencing, so no problem their neither. The Xetex XC6204 goes for about 0.77 EuroCent at Farnell.

: Based on what the FAE told me the CR2 may go away. Apparently what they are : coming out with next will be the successor to that family. Don't know if : the pinouts will change.

Even XC95XV(L) and XC2C have very similar pinout.

Bye

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply to
Uwe Bonnes

Wow, you don't ask for much. I suggest that you check around and see how many PLDs, other than the 20V10s or smaller, have been available for

10 years. I expect you will not find one! This is just not the way of very many semiconductors.

There are plenty enough to keep the family in production for a normal lifetime of 5 or 6 years.

You should take another look at both Atmel and Lattice. Don't go by some silly number like "market share". Check out the longevity of the parts they made 5 or more years ago.

If you are talking about power supply, then you can't use *any* of the newer parts. If you are talking about IO standards, then you can use LVTTL with nearly *any* family out there.

Did they give you a schedule by any chance? If they don't have a schedule then you shouldn't expect it within the year. Oh, yeah, don't expect it to be 5 volt tolerant. If you only need LVTTL, then you should be ok, but all newer devices are 5 volt phobic.

I very seriously doubt that Xilinx is going to replace the XC2 line. It is not very old at all. The XPLA3 line is 5 volt tolerant (sort of) and no new process can replace that. Where did you hear this new line?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
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Arius - A Signal Processing Solutions Company
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Reply to
rickman

Hey, a Lattice guy.

What you say makes a lot of sense, and the market share numbers are interesting. Yes, I am in Portland right by you. I'll give the rep a call. You are right I should probably take a look at Lattice before I decide. They are the 3rd big player.

Thanks, Chris.

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VHDL/VERILOG

Reply to
Chris_S

The FAE told me that the next CR, say CR-III, will be very low voltage again like 1.5 or 1.8. That would certainly not be a replacement for the XPLA3 family since it is 3.3V. It is far more likely it would replace the CR-II family. At least that's what the Xilinx FAE thought.

Chris.

Reply to
chris_s

Perhaps "replace" is a poor word to use here. None of these families "replace" another. They will still make the older family and the new one will never fill the same socket since it uses a different voltage.

But I seriously doubt that Xilinx is spending a lot of time or effort on updating the CR2 family since they are really still shiny new. This may be something in the works, but I doubt that you will hear it announced for 6 months or more and chips are not likely for a year.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
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Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
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Frederick, MD 21701-3110                 301-682-7666 FAX
Reply to
rickman

Take a look at the LC4000. They are 1.8 volt core, but come in several versions with internal LDOs to allow operation at other voltages. The ZC (or CZ) version with no LDO is the ultra low power one.

If you don't need ultra low power, but need a larger part at a decent price check out the LC5512Mx. Again this is 1.8 volt (MC) internal core with 2.5 (MB) and 3.3 (MV) volt versions available. They quoted me (after some beating about the head and shoulders) a *much* better price than the Xilinx parts.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX
Reply to
rickman

I'm looking through the Lattice stuff right now. Which family would be the equiv for the XPLA3? They have quite a few families.

Chris.

Reply to
chris_s

Can they elaborate on the 'out soon', in this industry, that can reach to the end of 2004 :)

This sounds a little mangled, and someone from Xilinx may enlighten us. It may be that the 'new' CoolRunner is the XC2 family ?

The XC2 is so new, only the XC2C256 gives web supply hits.

Once released, a device will only go obsolete if volumes get too small, or the FAB line closes. The latter happened to Lattice and Xilinx, but only affected design lines they purchased.

-jg

Reply to
Jim Granville

Not entirely - the new Lattice devices offer 5V tolerance, but they also spec 'no more than 32 IO' at a time. Strange spec, how does one IO 'know' the state of another ?!

On some devices the IO tolerance is spec'd also CORE relative, so you can get caught if your IO power is present, and the core voltage is not!

Lattice appear to be using on-chip regulators, so the multi-rail dance is showing signs of simplifying. The regulator is a bit 'ordinary', so the Icc goes up on those variants. There are uC being released with regulated core voltages (eg AT89C51ED2) so that is a sensible solution, esp for the smaller CPLD's

-jg

Reply to
Jim Granville

Exactly which new families did not "make it" in the market? I don't see any reason to expect the LC4000 (which is what I believe you are calling Mach 4000) will not be here as long as any other PLD family. This is a sound part and has some very good features. As to price, I have gotten much better pricing on the Lattice parts than I have on the Xilinx CR ones. Once the size gets up a bit, the CR parts get very, very expensive.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
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Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX
Reply to
rickman

Where did you find the sink current info/value - from the FAE ?

I get this info from their Data:

#5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed. # #IIH 2 Input High Leakage Current # 3.6V < VIN = 5.5V, Tj = 105°C 3.6V, and watch what happens :))

-jg

Reply to
Jim Granville

I was told this by both an FAE and support by email. I am sure both are just parroting whatever is the original source of the info. I could not get them to give me any more detail, such as what effect a series resistance or other source impedance would have on the spec.

From the FAE... "You are correct, the 5512MB does have a limit of 64 IOs that can be driven above 3.6V. This is due to the leakage current that appears when an input is biased above VCCio. They need to keep the total amount of this leakage current below a certain number and that worked out to 64 IOs."

From support... "The 64 IOs 5V restriction is a reliability requirement for EE9 technology to ensure that we meet oxide FIT rate requirement."

You could do your own testing on a device, but how would you know that this will be consistant across future versions of the device? It is not at all uncommon for a company to alter their process while keeping the original published spec. Xilinx has discussed this recently on the SpartanXL. While they maintained all the publised specs (and improved some), anything that you have tested in the past may no longer function that way.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX
Reply to
rickman

Thanks - Now, that support reply makes sense, the first one is a mangled version of the second one.

If it is actually an oxide stress FIT parameter, then the 64 is an arbitary number, and failures are related to IP * Time products. The Oxide stress FIT of a single IP is finite, with more IPs you just ramp the statistical chances of ONE having a failure.

It would be nice if they published more info on this, like the voltage/FIT slope, and just what the actual FIT value is, so in design you can decide on additional clamping, or if other measures are needed.

There are processs where the gate-oxide thickness can be varied across the die ( and even thresholds, within a gate oxide ), but perhaps they have not made it to PLDs yet ?

-jg

Reply to
Jim Granville

Do you have any comments on Chris's mention (FAE attributed IIRC) that there is a new Coolrunner soon to replace the CR2 ?

- or is it more a complementary family, like the lattice 4000/5000 series ?

- or just an urban myth ?

-jg

Reply to
Jim Granville

Reply to
Peter Alfke

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