Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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phase noise in NCO
Hello, I want to make a phase measurement at 100MHz with a NCO at 200+ MHz This NCO will have a 32 bit phase accumulator and a 32 bits phase offset. The output will be only one bit. I will use a phase...
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20 years ago
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Copy Altera Config EPC2 via JTAG?
I have the need to duplicate the code that is in one Altera EPC2 to another one on an identical bit of hardware. The device has a 10 pin JTAG connector. Is there a low cost, easy way to suck the bits...
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20 years ago
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Re: Dynamic Reconfiguration, Contentions
More than one column. There is a load multiple column command. This loads columns that are contigous to each other. Usually the reconfiguration process loads one column on the left side of the die and...
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20 years ago
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Re: eCOS port for NIOS
have you tried uCOSII ?
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20 years ago
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std_logic_vector type port doesn't work after synthesis.
Hi I encountered a problem during synthesis and I really hope I can get your help. I declared a std_logic_vector(7 downto 0) (inout type) entity port in my VHDL program. In the testbench, I will try...
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20 years ago
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wired downloading bitstream to spartan2
HI, I have a Avnet Spartan2 board, if I download the the .mcs (prom file) comming with the board to it, it seems everything is OK. Then I build my design, went through the implementation flow, and I...
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20 years ago
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Re: Interfaces in Handelc
Hey guys, I'd recommend that splitting up your design into smaller projects is not the way to proceed, IMHO. You are just going to complicate your design and make it more difficult to simulate. How...
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20 years ago
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Re: [DLL usage Virtex/Spartan-II] HowTo drive CLKDV Div 2 off Chip
Be carefull. Usually when you instantiate a ibufg, you are actually instantiating a IOB configured as an input, and a bufg. You only want to use an IOB as the input and make sure it is loc'd to a clk...
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20 years ago
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Re: How to Tristate!!! when not reading
dataOut 'Z'); Muhammad Khan wrote: > HI Fellows, > The process given below is to read and write to Vertex device ( only > vhdl part is shown here not C ). I want to tristate SR_DATA_IO_int > when not...
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20 years ago
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Re: User Core OPB Problem (EDK3.2)
The ssp0 core has a mir interface within. You need to assign the addresses for the mir registers. I.E: BEGIN opb_core_ssp0 PARAMETER INSTANCE = opb_core_ssp0_1 PARAMETER HW_VER = 1.00.b PARAMETER...
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20 years ago
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ISE 5.1/5.2 Error
I wrote a program in vhdl with ISE 5.1 and when I try to simulate the post translate VHDL model or Post Map or Post place and route, I receive the follow error: ERROR: Hidden remap failed Reason: None...
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20 years ago
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GSR
Gentlemen: I have a situation where some of my compatriots want to be able to reset a Virtex2 in order to reload the program from the 18V04 chips. Generally, they are going to want to do this after...
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20 years ago
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Re: Altera licenses
I guess everyone is trying to download Quartus 3.0 at once during daytime. The file weights 137MB and has just been released, so a busy server is understandable today. I got it late last night and the...
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20 years ago
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Beta sites needed
I'm part of a new startup, Zeidman Technologies, that's developing a new software tool, called SynthOS, that will automatically generate an RTOS that's optimized for your hardware. This RTOS has a...
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20 years ago
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Re: Pulse stretching
The decision on what works "better" is dependent on why you need to stretch the pulse. If you need a signal that's big enough to be sensed in a different clock domain, an "acknowledge" can be brought...
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20 years ago
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