Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
Re: Quartus warning in NUMERIC_STD.vhd
I agree. A bad assignment to a null vector will cause other errors. A null vector declaration alone is innocuous. If one bit is 0 to 0 then no bits must be 0 to -1 Let's see: -------------------...
2
|
20 years ago
|
2 | |
|
|
XML for VHDL documention and structural description of Hardware SoC
Hi VHDL GNU men, Amontec is interested to build an auto-documentation of our VHDL libraries, cell-by-cell. The documentation will stay basic, like : general description port description generic...
—
|
20 years ago
|
— | |
|
|
PROM JTAG download cable for Xilinx Spartan II + Webpack
Hi, I have a PROM (XC18V02) set up on my Spartan IIE evaluation board. I'm developing under Xilinx ISE 5. I'm wondering what would be the simplest JTAG cable I could build (or buy if real cheap) to...
—
|
20 years ago
|
— | |
|
|
how can I use a signal defined in one Architecture to another Architecture
Hello everybody, I want to use the signal defined in one architecture in VHDL to another architecture. I have two architecture in the same .vhd file and I am using Component mapping. I required the...
3
|
20 years ago
|
3 | |
|
|
Make file ...........Help Please
Hi Fellows, How can I synthesize multiple file one by one using xilinx compiler in MAKEFILE script. I have done using only one file but when I enter multiple files in "VHDL= ....." field thenI get the...
1
|
20 years ago
|
1 | |
|
|
Synplify and then Quartus
Hi, I have been using Quartus II 2.0 for all my synthesis and fitting needs for the APEX20KE device I have on my prototype board. I hear that Quartus is not an efficient synthesizer compared to...
1
|
20 years ago
|
1 | |
|
|
How to change Read Only Constraint to Read-Write
Hi, I am using singal of 32 bit's lenght in my .vhd file and I am compiling using Makefile. I have also defined a UCF file. My UCF file is generating error when run ngd build using Makefile. The error...
3
|
20 years ago
|
3 | |
|
|
cascaded DLL's in VirtexE, routing problems
I do a rather heavy cascaded clock division/multiplication using DLL's in a VirtexE and have problems with routing resources from/to the dll's. I do not have enough resources to route all LOCKED...
—
|
20 years ago
|
— | |
|
|
Xilinx price question
Hi, I've just had a look at marshall's (avnet) web site and it seems that the Xilinx Virtex II XC2VP100 is $11512. Did I miss something or lost some zeroes ? Is it that kind of price ? Thanks a lot...
—
|
20 years ago
|
— | |
|
|
Leonardo changes name of lpm megafunction
Hey, I'm trying to create a 20-bit pipelined adder using the lpm_add_sub megafunction, but when I try and compile my project in leonardo it changes the name in the .edf file from lpm_add_sub to...
—
|
20 years ago
|
— | |
|
|
Re: Books
Hi, Have a look at Ben Cohen's book. That's my choice. Please visit HTH, Ajeetha
—
|
20 years ago
|
— | |
|
|
Re: scaling fixed point fft
You didn't mention the radix of each stage. Divide by 4 is too much if it is a radix2 butterfly. If it is radix 2, the gain is at most 2, not 4. The max output from an FFT occurs when all the input...
—
|
20 years ago
|
— | |
|
|
Re: clock management on SPARTAN2
: Hi, : I am having trouble with the GCLK feature in my design. : Basically my code is a 4 way handshaking protocol between my PC and : the FPGA on one hand and another 4 way handshaking with an :...
5
|
20 years ago
|
5 | |
|
|
Re: About BRAM in VirtexII
If you see it in the simulation then there is a good chance that it is going to happen in the hardware. If you see it in hardware you may be able to reproduce it in the simulator. That is life. Steve
1
|
20 years ago
|
1 | |
|
|
Rant mode ON
I need to vent a little steam. So at risk of making myself look stupid (or more stupid) I will do it here. I have been trying to get the Quartus 3.0 software and a license since last Thursday. I tried...
10
|
20 years ago
|
10 |