I want to make a phase measurement at 100MHz with a NCO at 200+ MHz This NCO will have a 32 bit phase accumulator and a 32 bits phase offset. The output will be only one bit. I will use a phase comparator followed by an integrator (digital or analogic if needed). At 100MHz the NCO output will be very very noisy but if I integrate it for a rather long time (10ms) will it have a 0 mean ? Can I implement this in an FPGA or should I use a DDS chip (AD9854) ? Where can I find some maths on this subject ?
A 32 bit accumulator will have very, very low noise in the digital domain due to the high resolution. If you need to convert this to analog, you will find significant noise from the discrete time sampling. However the noise level will be affected by your filter.
The phase noise is an AC measurement so it will not integrate to zero over time. With a 32 bit phase accumulator, I expect nearly all of your phase noise will be due to your osciallator source giving time error of the samples.
Rick "rickman" Collins
A 1-bit output will give you NCO phase noise that has a range of 5nS peak-to-peak based only on the single bit output. The only exception to this value is when you run at a fractional value such as 100 MHz from the
200MHz clock where the accumulator acts as a divide-by 2. [I guess all frequencies will be a fractional relation - 1329046/2^32 is still a fraction. The arguement applies to small whole number fractions such as
3/16.] The way to get good performance from the system is to use the full DDS - an NCO with a D/A such as those very nifty Analog Devices parts.
If you compare the phase to a noise-free reference that is precisely the desired frequency, the low-passed output of the phase comparator will conceptually be the phase offset between your NCO and the noise-free reference. I say conceptually because this is not a practical test. If you're trying to figure out of the phase noise is "lopsided," you should find the phase comparator output is some form of sawtooth. If the frequency is very close to a fraction of the 200MHz clocking frequency, your phase comparator output will appear to recover from a step function while the reality is that it's a very long sawtooth. Your frequency give you results with phase variations that are much closer in time where it's hard to see the longer term sawtooth characteristics beyond the very large, high frequency variations you see without the lowpassing.
The NCO can be implemented in the FPGA. You could drive a D/A with the FPGA though it's recommended that the D/A's clock be sourced direclty from your low phase-noise source rather than passing the clock through the FPGA. The DDS chips with integrated D/As are the best for this kind of thing.
Unfortunately, the maths are a little loose on the phase noise results. I've only seen textbook treatment of simple jitter: a sinusoidal phase variation. The Bessel function is a result of the Fourier of the
kind of form (ah, my kingdom for an ohmega, phi, or alpha on this keyboard). The Bessels give you only a slight idea of what happens in the NCO realm. The investigations I did went through a theoretical setup I described above. Determine the time domain of the phase comparator output from your NCO compared to the "ideal" noise-free reference mathematically. The pattern will repeat when the NCO accumulator values repeat which will happen at least every 2^32 cycles. This time-domain result might be what you seek. The frequency domain interested me, so I took the FFT of the time domain.
If you're only interested in close-in phase noise and higher frequencies are a non-issue, there are ways to increase the peak-to-peak phase noise while decreasing the close-in phase noise. A google on "MASH" and "frequency synthesis" might bring up results on that advanced subject.
Do you need to know the spectrum of the noise, or just the peak to peak value?
I sometimes find myself in the situation of having to work out the spectral characteristics of the phase noise (jitter) of the msb of a phase accumulator. E.g. if I am using a post-NCO PLL (as Peter A. suggested) then I only care about the phase noise components at offset frequencies less than the loop bandwidth of the PLL.
I don't know of a closed form expression for spectrum of the noise, but it's trivial to work out the spectrum with a spreadsheet (once you know how). This is much easier that trying to measure the spectrum in the lab. (Reply if you are interested in the method.)
BTW, Peter's trick of reducing the jitter by a factor of 4 (I assume) relies on using a 4 phase clock. This is almost certainly worth the effort if you are trying to reduce the jitter. I have a worked example that uses a 2 phase clock (actually it uses both edges of a single clock) in my free fractional N divider generator, at this web site:
(Note: some web proxies don't like domain names with underscores.)
I'm trying to have an almost all digital solution. I would rather use a DDS rather than a PLL as I'm not generatin a frequency. I just want to lock on the phase. (I have the reference frequency) I'ts a kind of DLL...
Sounds challenging : If I have this right You have 100MHz 'incomming' (hopefully very clean and phase stable :) You want to lock to 0.1%, (or 10ps), nominally 200MHz local Osc You can tolerate longer lock acquire times
Analog Phase locked loops work because they integrate the phase-magnitude errors,
- In a digital system, edge resolution of 10ps may be just possible, but I'm not sure you can get any error-proportional siganl. Go-right/Go-Left control is likely to be swamped by the phase-noise of the DDS signal.....
I've used the Ad9954 DDS and the phase noise is about -140dBc/Hz @
10KHz 0ffset. Your clk ref needs to be better than that if you want an accurae measurement. I used a DRO for the reference and an Agilent E5500 phase noise test set to measure it. Download the Analog Devices dds tutorial for all the math involved.