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- Charles Krinke
July 7, 2003, 9:07 pm

Gentlemen:
I have a situation where some of my compatriots want to be able to reset
a Virtex2 in order to reload the program from the 18V04 chips. Generally,
they are going to want to do this after they have loaded a new image into
the eprom's and they want to do it under program control.
Would I be correct in assuming that all they need to do is instantiate
glbl.v in their design and assert the GSR signal hi? At that point, the chip
should tri-state that same assertion and all the other signals, read the
eproms and start afresh?
Charles
I have a situation where some of my compatriots want to be able to reset
a Virtex2 in order to reload the program from the 18V04 chips. Generally,
they are going to want to do this after they have loaded a new image into
the eprom's and they want to do it under program control.
Would I be correct in assuming that all they need to do is instantiate
glbl.v in their design and assert the GSR signal hi? At that point, the chip
should tri-state that same assertion and all the other signals, read the
eproms and start afresh?
Charles
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