std_logic_vector type port doesn't work after synthesis.

Post your code. Your output enable logic is likely the problem.

-- Mike Treseler

Hi ,

Thanks for your reply.

I even tried to initialize this inout port to all 0, but it still shows "UU" when I start simulation. During pre-synthesis simulation, the initial value of DATA is also "UU", but it changes to correct value after assignment take effect in the test bench.

I try to figure out which one is driving this DATA port when its value is changed. But I don't know how to do this in Active HDL. The break point is located in the lsi_10k library and I can't trace it until the program control comes back to my program.

Thanks.

Liang

Here is my code:

--design.vhd library lsi_10k; use lsi_10k.all; ... entity DESIGN_UNIT is

port( DATA : inout std_logic_vector (7 downto 0) := "ZZZZZZZZ"; ...);

end DESIGN_UNIT;

--testbench.vhd entity test_bench is end entity test_bench;

architecture behav of test_bench is signal DATA: std_logic_vector(7 downto 0); signal Clock: bit :='0'; ... begin DUT: entity DESIGN_UNIT port map(DATA, ctl_data, ctl_op, Reset, Clock);

simulation: process is begin clock > I declared a std_logic_vector(7 downto 0) (inout type) entity port

Hi,

There doesn't seem to be an architecture associated with your DESIGN_UNIT entity.

"UU"