I encountered a problem during synthesis and I really hope I can get your help.
I declared a std_logic_vector(7 downto 0) (inout type) entity port in my VHDL program. In the testbench, I will try to assign some value to this port. But after synthesis using Synopsys Design Compiler, I found this port wouldn't accept the value from signal assignment in the test bench and the value of this port becomes "XX".
BTW, even I initialize this port to "ZZZZZZZZ" in the entity definition, it still doesn't work.
I even tried to initialize this inout port to all 0, but it still shows "UU" when I start simulation. During pre-synthesis simulation, the initial value of DATA is also "UU", but it changes to correct value after assignment take effect in the test bench.
I try to figure out which one is driving this DATA port when its value is changed. But I don't know how to do this in Active HDL. The break point is located in the lsi_10k library and I can't trace it until the program control comes back to my program.
Thanks.
Liang
Here is my code:
--design.vhd library lsi_10k; use lsi_10k.all; ... entity DESIGN_UNIT is
--testbench.vhd entity test_bench is end entity test_bench;
architecture behav of test_bench is signal DATA: std_logic_vector(7 downto 0); signal Clock: bit :='0'; ... begin DUT: entity DESIGN_UNIT port map(DATA, ctl_data, ctl_op, Reset, Clock);
simulation: process is begin clock > I declared a std_logic_vector(7 downto 0) (inout type) entity port
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