how can I use a signal defined in one Architecture to another Architecture

Jul 09, 2003 3 Replies
M

Hello everybody,



I want to use the signal defined in one architecture in VHDL to another architecture. I have two architecture in the same .vhd file and I am using Component mapping. I required the result of calculation of a signal to be used in second architecture. Can any one tell how to defined signal so that it is globally visible to other architectures.



Regards



Khan


Vote
Twitter Facebook LinkedIn
M

Hello Muhammad,

this is a common question.

The clean way for handling this is to feed the signal through the port maps.

Regards, Mario

---------------------------------------------------------------------- Digital Force / Mario Trams Mario.Trams@informatik.tu-chemnitz.de Mario.Trams@wooden-technology.de Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr Dept. of Computer Science Tel.: (+49) 371 531 1660 Chair of Computer Architecture Fax.: (+49) 371 531 1818 ----------------------------------------------------------------------
Vote
Twitter Facebook LinkedIn
J

Hi Khan, If you declare a signal in a package and you include the package then the signal can be globally used by all architectures that reference that package. This is for simulation only and will not work for synthesis.

Jon

Vote
Twitter Facebook LinkedIn
K

This will work for synthesis in Synplify Pro 7.3.

Vote
Twitter Facebook LinkedIn

Join the Discussion

Have something to add? Share your thoughts — no account required.

Didn't find your answer?

Ask the community — no account required