Udayan wrote: : Hi,
: I am having trouble with the GCLK feature in my design.
: Basically my code is a 4 way handshaking protocol between my PC and : the FPGA on one hand and another 4 way handshaking with an : asynchronous chip on the other.
: I am providing a clock to the system through the GCLK0 pin using an : oscilltor.
: I further require edge tests on three lines that I receive from the : computer and the chip - which means they are inferred as clock : signals.
: A total of 4 clocks.
: However when I try to implement the design the engine complains that : my design is too large
: Number of GCLKs: 6 out of 4 150% : Number of GCLKIOBs: 1 out of 4 25%
: I cannot understand why this is so. I take the input from my CLKIOB
Look at the synthesis report (*.syr) and at the graphical representation of your circuit ("View RTL Schematics"). It will give you a glimpse of what is going on. Then rethink the way you wrote your HDL implementation. In the synthesis report, the "Clock information" might be the most important thingto look at.
Bye