If you see it in the simulation then there is a good chance that it is going to happen in the hardware. If you see it in hardware you may be able to reproduce it in the simulator.
That is life.
Steve
You haven't really given us enough information - you should post a little more about the problem; are you getting an error or warning from the simulation, and if so, what exactly is happening around the time of the error. Also we need to know a little more about your application.
Are you using the same clock for both ports of the ram (i.e. are CLKA and CLKB driven from the same BUFG). If so, there is one condition where reading and writing to the same address is legal - if the port doing the write is set to "READ_FIRST" (an attribute set on the RAM), then the data returned from the read port is the previous contents of the RAM. You also don't specify if the two ports of the RAM are the same widths.
That being said, you say that you have "logic to avoid hits over the same address", meaning you are (trying to) guarantee that you never attempt a simultaneous read and write to the same address. In the past, we have had some problems with the simulation models of the CoreGen RAMs; we definately had situations where the model would erroneously declare a read/write conflict (i.e. there have been bugs in the simulation models in the past). So, the question is, are you sure there is no conflict. It should be easy to verify by looking at the waveforms (capuring all the inputs and outputs of the Dual Port RAM in question). If you are getting an error, look at the waveforms around this error to determine if you are indeed writing and reading to the same address (or similar addresses) at the same time. Remember, if the port wirths of the two ports are not the same, then the "same address" from the point of view of the RAM is not simply ADDRA == ADDRB; if portA is 16 bits wide and portB is 4 bits wide then a contention exists when ADDRB/4==ADDRA
Avrum
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