how can I simulate the vhdl and verilog mixed design in modelsim?

Question

Hi, all ,

I am using ISE6.2 and modelsim5.8b. My design is composed of two modules, one is VDHL design ,and the other is verilog design. Now I want to combine them together in a top level file (in vhdl) and simulate the whole design. Can I just instantiate the verilog design module with a compoenent in the top file and write a testbench for the top file. I have done this , but it fails when binding the verilog module (rx_backend). # ** Failure: Default binding had errors for entity 'rx_backend' on the component declaration of line 220. See the compiler messages. Could u give any idea on how to do the mixed vhdl and verilog design and simulation? Many thanks.

Jimmy

Steven · Accepted Answer

following is the sim script from xapp134, which runs mixed v & V simulation.

Nothing is special. You need compile all files before sim them.

vlib work vmap work work vcom -93 brst_cntr.vhd vcom -93 cslt_cntr.vhd vcom -93 ki_cntr.vhd vcom -93 mti_pkg.vhd vcom -93 rcd_cntr.vhd vcom -93 ref_cntr.vhd vlog mt48lc1m16a1.v vcom -93 sdrmc_state.vhd vcom -93 sys_int.vhd vcom -93 sdrm_t.vhd vcom -93 sdrm.vhd vlog tb_sdrm.v vsim work.t_sdrm view signals structure wave source source verwave.do run 3000 ns

Hope it will help.

Steven Yu

pablo aimar · Answer

##############Hi,  Earlier i had this problem buti have solved it. What you can do is first installvhdl version, then copy vhdl folder  fromC:Modeltech_xe_starterxilinxhdlto different location. Then uninstall the modelsim and again installthis time for verilog, this time you haveC:Modeltech_xe_starterxilinxerilogNow copy the vhdl from previous location to this locationC:Modeltech_xe_starterxilinxIf you now open the modelsim you have both libraries(verilog and vhdl)and you can start mixed language simulation.Note: This applies only to Free Modelsim XE edition(xilinx).Regardsrao

how can I simulate the vhdl and verilog mixed design in modelsim?

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