Hi, I am having a problem during the synthesis (with ISE) of my design, with the following error message : "ERROR:HDLCompilers:88 - Parameter 'INIT' does not exist in module 'FD'" Here are some details on this design : I am using a component I wrote in vhdl which instanciates a KCPSM 3 with a program rom.This component synthesizes perfectly, but when I'm trying to synthesize the top-level design, XST crashes.

Actually, in the top-level, I am using other modules, written in verilog by Xilinx, which uses FD's.I think the problem is that the module definitions (in verilog) for synthesis black boxes for theses "FD" modules does not match with the corresponding component declarations in vhdl of a FD flip flop, because in vhdl this declarations INCLUDES a generic, which is the init value "INIT"... How can I solve this problem?

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Below, I have included example code on how to infer or instantiate a FD in VHDL and Verilog. You need to use a defparam for the initialization string in Verilog. These examples are taken from the Libraries Guide that can be found at:

-- go to

formatting link

-- click on "Documentation" on the top black bar

-- click on "Software Manuals" at the top of the page

-- click "6.1i SW Manuals" at the top of the page

-- click "HTML Collection"

-- expand "Libraries Guide" on the left

-- expand "Design Elements"

-- highlight "FD"

Cheers, Shalin-

VHDL Inference Code architecture Behavioral of fd is begin process (C) begin if C'event and C='1' then Q user_Q, C => user_C, D => user_D);

Verilog > Hi,

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Shalin Sheth

An important detail that I ommited : obviously when you use a KCPSM 3, the program rom is described in HDL (here in VHDL) using attribute definitions to describe the contents of the rom, that's the "INIT" statements I am talking about. My problem is that there seems to be some kind of non-compatiblity with VHDL mixed with Verilog..

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