KCPSM3+vhdl+verilog

Below, I have included example code on how to infer or instantiate a FD in VHDL and Verilog. You need to use a defparam for the initialization string in Verilog. These examples are taken from the Libraries Guide that can be found at:

-- go to

-- click on "Documentation" on the top black bar

-- click on "Software Manuals" at the top of the page

-- click "6.1i SW Manuals" at the top of the page

-- click "HTML Collection"

-- expand "Libraries Guide" on the left

-- expand "Design Elements"

-- highlight "FD"

Cheers, Shalin-

VHDL Inference Code architecture Behavioral of fd is begin process (C) begin if C'event and C='1' then Q user_Q, C => user_C, D => user_D);

Verilog > Hi,

An important detail that I ommited : obviously when you use a KCPSM 3, the program rom is described in HDL (here in VHDL) using attribute definitions to describe the contents of the rom, that's the "INIT" statements I am talking about. My problem is that there seems to be some kind of non-compatiblity with VHDL mixed with Verilog..