Port mapping a Verilog component in a VHDL design

Dear Sir or Madam,

I have the following problem:

I have a simulation component which is written in Verilog (not a trivial one which could be translated to VHDL). My toplevel design and all other components are written in VHDL.

My question:

Is it possible to include this Verilog component in my VHDL top level ?

What about the types std_logic / std_logic_vector ? Can I connect the inputs and outputs of the Verilog component to signals of these types ? How do I define it in the VHDL top level ?

I do not know if such thing is possible but I would be very thankful for any information about that.

Kind regards Andrés Vázquez G&D System Development