How to simulate testbenches using the ISE simulator in linux

Two choices:

1. Load the windows version of ISE
2. Buy a modelsim SE floating license.

-- Mike Treseler

Hi Ankit,

I am afraid that Fedora 6 is not a supported OS for Xilinx SW. Although since you are able to get all the other SW to work fine and it is only ISE Simulator that is giving you trouble, let us see if we can come up with a fix.

Thanks Duth

Hi Ankit,

We might have something that could work. Can you try the following:

mv $XILINX/gnu/gcc/3.2.3/lin/bin/ld $XILINX/gnu/gcc/3.2.3/lin/bin/ ld.old ln -s /usr/bin/ld $XILINX/gnu/gcc/3.2.3/lin/bin mv $XILINX/gcc/3.2.3/lin/i686-pc-linux-gnu/bin/ld $XILINX/gcc/

3.2.3/lin/i686-pc-linux-gnu/bin/ld.old ln -s /usr/bin/ld $XILINX/gcc/3.2.3/lin/i686-pc-linux-gnu/bin

If this is a 64 bit machine, please use lin64 instead of lin for the path.

Please let me know if this does not work. We might have to do the same for collect2 as well.

Thanks Duth

are you sure your test bench is correct ? did you purge the projects files ?

I have a linux station and webpack ISE9.1.03i, synt. and simul, impact, chipscope... are more stable than the same tools on the same station with windows XP (no freeze while xst or par, impact/usb works fine...)

see console and log and add the missing tools / libraries / access rights...

Hey Duth..

Hi..Thanx for taking time and replying to my query..I have been trying to run the command you mentioned in your posts but this what it says..

[ankit@localhost Xilinx91i]$ mv $XILINX/gnu/gcc/3.2.3/lin/bin/ld $XILINX/gnu/gcc/3.2.3/lin/bin/ mv: cannot stat `/gnu/gcc/3.2.3/lin/bin/ld': No such file or directory Plus i am a liitle new to linux so pleas dont mind if 1 of my queries turn out to be stupid.. I ran these commands in the terminal i am hoping thats where i should have run them..Or i should have executed these in the TCL shell..

Please do help me out of this dilemma as my mentor is admanat that i run Xilinx on linux..

Waiting for your reply..

Regards Ankit

I've had troubles using the ISE simulator as well under a "non-supported" Linux distribution. As only the GUI components seem to behave badly, I ressorted to writing a bash script to start run a simulation and display the results in the standalone isimwave tool. I can elaborate on that and post the script if anyone is interested.

Best regards,

Laurent Pinchart

It seems like your $XILINX variable is not set. It should point to directory where your Xilinx software is installed. So the $XILINX variable expands to something empty and you end up with the path /gnu/ gcc... and mv does not find ld.

You can check the (any) variable with the command 'echo $XILINX'.

Try 'echo $PATH', it should print you out the search path for executable applications.

To set it in a bash shell use the command 'export XILINX=

A second problem in your command seems to be that you forgot the ld.old for the second parameter of the mv command.

Check out 'man mv' in your shell and it will tell you what it is doing.

Cheers,

Guenter

Hi Ankit,

Please follow the recommendation that Guenter provides, what you are seeing here are just user errors of not setting up the environment correctly. I would also recommend that you try to have a linux specialist assist you out as well, as it may make this process a lot smoother. Additionally you can also try Laurents recommendation of just loading isimwave after simulation.

Thanks Duth

1. Complain to Mentor for penalizing Linux users!

yes I know there is Modelsim LE but that is just ^$&%£") Verilog only :-(

Hans

Hi Laurent

I think it would be really great if you could tell the exact bash script because i would not mind that too..My aim here is to run xilinx on linux it does not matter how it is done..

@ Duth i will try that also let us see what happens...

Regards Ankit

Hi Ankit,

Ok. Here is a quick howto. I assume you have a basic knowledge of bash scripting. If not, there are plenty of documentation available online.

1. Directories and file names

The examples below are based on the following project directory hierarchy.

/bench /vhdl VHDL test benches /verilog Verilog test benches /rtl /vhdl VHDL source files /verilog Verilog source files /sim /rtl_sim /bin Simulation scripts /log Simulation logs /out Simulation results /run Simulation resources /syn /xst /bin Synthesis scripts /log Synthesis logs /out Synthesis results /run Synthesis resources

Only VHDL and Verilog sources can be simulated this. Coregen can generate VHDL or Verilog simulation modules for (some) IP cores, and schematics can be converted to VHDL or Verilog as well.

If you want to adapt the hierarchy to your needs (or even flatten everything out), you will have to modify the simulation script.

1. Environment variables

First of all, make sure your environment variables are up-to-date. The Xilinx binary and shared library directories should be accessible through $PATH and $LD_LIBRARY_PATH. If you allowed the Xilinx ISE installer to modify your system configuration (in /etc) this might be done already.

Check the $XILINX environment variable.

$ echo $XILINX /opt/xilinx/ise9.1i/

If the variable is not set, you can just source the configuration script (change the path to match your ISE installation directory).

$ source /opt/xilinx/ise9.1i/settings.sh

You will have to repeat this step for any shell instance you want to work with. You can alternatively add the above line to your bash startup script (.bashrc or .bash_profile).

1. Writing the test bench

The entity under test (EUT) must be instantiated in a portless top-level entity that will drive the EUT inputs. I usually write tests in VHDL, but you might be able to convert graphical waveforms into VHDL/Verilog code. I haven't tested this myself.

The simulation script assumes that your top-level test bench entity is named ${module}_tb (for instance, if the EUT entity is named counter, the top-level test bench entity should be named counter_tb). This can be overridden when running the simulation script, but it's a good idea to stick to a coherent naming if you have no reason to do otherwise.

1. Preparing the simulation resources

Now that your development environment is ready, you will have to prepare the simulation resource files.

The simulation script goes in sim/rtl_sim/bin. As the news server doesn't seem to like attachments, I included it inline. Let me know if it comes out badly.

---------------- sim.sh -------------------- #!/bin/sh

set -e

if [ $# -lt 1 ]; then self=`basename "$0"` echo "Usage: ${self} [options] module" exit 1 fi

do_compile=true do_wave=false entity=

while [ $# -gt 0 ]; do case $1 in -no-compile) do_compile=false ;; -wave) do_wave=true ;; -entity) entity=$2 shift ;; -*) echo Invalid argument $1 exit 1 ;; *) module=$1 ;; esac

shift done

if [ x${entity} == x ]; then entity=${module}_tb fi

if $do_compile; then vhpcomp -intstyle ise -work work=../out/work -prj ../run/${module}.prj fuse -work work=../out/work -top ${entity} fi

../out/work/${entity}/lin/xsimbhv_${entity} -tclbatch ../run/${module}.tcl \ -wavefile ../out/${module}.xwv

if $do_wave; then isimwave ../out/${module}.xwv & fi

-----------------------------------------------

Command-line simulation requires a project file (.prj) listing the VHDL/Verilog source files and a simulation script (.tcl) with the simulation commands.

Here are a sample project file and simulation script that goes in sim/rtl_sim/run.

---------------- sdclk.prj -------------------- vhdl work ../../../rtl/vhdl/sdclk.ent.vhd vhdl work ../../../rtl/vhdl/sdclk.beh.vhd vhdl work ../../../bench/vhdl/sdclk.test.vhd

-----------------------------------------------

---------------- sdclk.tcl -------------------- scope /sdclk_tb/

ntrace select -o on -n sd_frequency ntrace select -o on -n sd_stop ntrace select -o on -n sd_enable ntrace select -o on -n sd_clk_in ntrace select -o on -n sd_clk_out

ntrace start run all quit

-----------------------------------------------

The project file is pretty self-explanatory. Each line adds a source file to the simulation. The first keyword is the source file language, the second keyword the library which the source will be compiled into, and the third keyword is the source file path and name.

The simulation script select signals that will be recorded in the output waveform (ntrace directive) and start the simulation. The scope directive can be used to navigate in the design hierarchy and select internal signals.

More information on the ISE simulator and the simulation script commands can be found at

1. Running the simulation

The simulation script usage is as follows.

------------ Sample simulation session ---------- $ ./sim.sh

Usage: sim.sh [options] module

-entity Top entity name. Defaults to module_tb.

-no-compile Don't compile the sources. Useful if you modified the simulation script and want to rerun the simulation without recompiling the sources.

-wave Automatically launch the waveforw viewer upon completion.

$ ./sim.sh -wave sdclk

Compiling vhdl file "rtl/vhdl/sdclk.ent.vhd" in Library work. Entity compiled. Compiling vhdl file "bench/vhdl/sdclk.test.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. Compiling vhdl file "rtl/vhdl/sdclk.beh.vhd" in Library work. Entity (Architecture ) compiled. Parsing "../run/sdclk.prj": 0.27 Codegen work/sdclk: 0.00 Codegen work/sdclk_tb: 0.00 Codegen work/sdclk/str_sdclk: 0.00 Codegen work/sdclk_tb/bhv_sdclk_tb: 0.00 Release 9.1.03i - ISE Simulator Fuse J.33 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. Building ../out/work/sdclk_tb/lin/xsimbhv_sdclk_tb Release 9.1.03i - ISE Simulator Engine J.33 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. This is a Lite version of ISE Simulator. Simulator is doing circuit initialization process. Finished circuit initialization process.

** Failure:Simulation successful (not a failure). No problems detected. User(VHDL) Code Called Simulation Stop

Simulation stopped when executing process: sdclk.test.vhd:stimuli on line 105 in file "bench/vhdl/sdclk.test.vhd"

-----------------------------------------------

The simulation script will use ${module}_tb as the top-level entity name. If your top-level entity has a different name, use the -entity option.

I hope this helps. I've been using the ISE simulator with success for some time now with command-line simulation. You should install ISE 9.1i (with the latest service pack) or newer, as ISE 8.2i has lots of simulation bugs that have been fixed in 9.1i (including crashes).

Best regards,

Laurent Pinchart

process.

Hi Laurent,

Thanks for helping out here. Just one comment in case you did not know. The -instyle ise switch is not needed if you are not inside ISE :). We just use this for out internal use for formatting the messages better to show in the ise console in case you were wondering.

Thanks Duth

Hi Laurent..

Thanx a lot for providing the bash script..But i have worked out of this problem i wasnt able to reply sooner because i was trying to overcome this problem which made me land up in another..I arranged for RHEL 4.0 and i installed Webpack 91i on it the compiler and simulator are working out fine but it is the IMPACT which is giving me the problem what happens is when i double click on IMPACT after checking everything and showing it is successfully checked till "Fit" it just hangs up and during installation the drivers script do not get installed that is the drivers cable do not get installed saying "kernel mismatch"..So is there a way out of this i have tried installing windrvr6.0 but some how it doesnt seem to work out if somebody could provide a better solution to this it would be really great...

Regards Ankit

[snip]

The -intstyle was a left-over from copy&paste operations. Thanks for pointing it out.

Laurent Pinchart

I clearly advice against using the Jungo WinDriver kernel modules. They bypass the kernel security model to expose resources that should be kept inside the kernel.

If possible, use an open-source FPGA/CPLD programmer.

Best regards,

Laurent Pinchart

Hi Laurent

I am ready to use it if you could provide me with a link from where i could download it i guess this is my last chance of running it..I am getting a little frustrated as i have not been able to run xilinx completely on linux..A little help can really help me out..Waiting for your reply..

Regards Ankit Anand

Hi Ankit,

There are several open-source projects out there. Which device are you targetting, and what programming cable are you using ?

Parallel-port cables are widely supported. The Xilinx Platform Cable USB is a bit of a problem, as Xilinx won't release any information regarding the protocol. There have been a few reverse-engineering efforts to understand how the cable works, and an open-source firmware replacement has been developed. It currently runs slower than with the Xilinx firmware, but at least it's usable.

Have a look at

for a S3E programmer working with the USB cable.

Best regards,

Laurent Pinchart

Hi Laurent,

Thanx a lot for providing the link i will definitely give it a try..I am looking to program the CPLD board using the the parallel port i will use JTAG..

Regards Ankit