Adding Verilog processing core to Viretx2Pro at ML310

New version of Xilinx ISE Foundation (7.1i) supports mixed design architectectures. So If you have one part of design in VHDL and other parts in Verilog you can it compile.

Regards, Amir

Chapter 4: Create and Import Peripheral Wizard of "Embedded System Tools Reference Manual"

"The OPB/PLB peripheral (top design entity) template is in VHDL only. This is because the underlying library elements are implemented in VHDL. The stub user-logic module template, however, can be in either VHDL or Verilog to support a mixed-language development mode."

Additional verilog files can be used by adding them to the *.pao file of the generated pcore.

Paul

sps wrote:

Thanx ppl.

Can I do something like we do with any spartan device, I mean without using anything(Processor,IPs,Buses), can I map my application on Virtex2Pro?

Thanx

Regards

sps