VHDL and ModelSIM question

Hi,

I have been trying to learn the "generic" statement in VHDL and as a result I have made the generic binary decoder (below) in VHDL. Note that both the encoded input A and decoded output Y are of type unsigned. Also in the "for" loop I have used "to_integer"

Then I have a top level file that instantiates this decoder with SizeIn =

8 and SizeOut = 256.

The design is synthesized and implemented without any errors on XST. However when I try to simulate the design using ModelSim I get warnings and errors such as -

# WARNING[1]: Types do not match for port A # WARNING[1]: A use of this default binding for this component instantiation will result in an elaboration error. # WARNING[1]: Types do not match for port Y # WARNING[1]: A use of this default binding for this component instantiation will result in an elaboration error.

** Failure: Default binding had errors for entity "top_architecture" on the component declaration of line 55. See the compiler messages.

I think this is because of type "unsigned" When I remove "unsigned" and make it type "std_logic_vector," I cannot use the "to_integer" in the "for" loop. XST does not synthesize and gives the following error

ERROR: HDLParsers:808 - to_integer cannot have such operands in this context

Any ideas? I am absolutely frustrated with VHDL right now :D. Maybe the best way would be to make it std_logic_vector and somehow get the same functionality of "to_integer" by some other function.

Thanks in advance for your help.

-Yash

************************************************************************* library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity generic_decoder is generic (SizeIn, SizeOut: integer); port ( Clock, Rst : in std_logic; A : in unsigned(SizeIn - 1 downto 0); Y : out unsigned(SizeOut - 1 downto 0)); end generic_decoder;

architecture arch_generic_decoder of generic_decoder is

begin

process (Clock, Rst) begin if (Rst = '1') then Y '0'); elsif (Clock'event and Clock = '1') then for N in 0 to SizeOut - 1 loop if (to_integer(A) = N) then Y(N)