How do I use the DDS core in a verilog flow?

take a look at core_name.veo (core_name.vho for vhdl) vit a text editor, these files have instantiation template for your core (all the param/generics and ports)

(replace core_name with your actual core name) have fun, Aurash

I tried that. The problem is that when you instantiate a verilog module it will implicitly refer to a ".V" file, which is the simulation model. It appears that only the EDIF file can be used for synthesis/place&route.

What am I misinterpreting?

xilinx_user skrev:

if I use coregen to generate a, for example, a memory block called "ram2kx8" I get from coregen:

ram2kx8.v: that is the wrapper you need to include in you synthesis and simulation. ram2kx8.veo: that is a file with an example of how to instatiate the module (cut-n-paste from this file as needed) ram2kx8.edn: the edif file need to be in a place where the place and route toold can find it

-Lasse

I am still having trouble.

I have a working directory called "exhaust." In this directory I have the following:

xyz.v sine_dds.edn

File xyz.v contains the following:

module xyz(CLK,WE,SCLK,WE,A,SINE); input CLK,WE,SCLK; input [4:0] A; output [20:0] SINE;

sine_dds sine_new( .DATA(DATA), .WE(WE), .A(A), .CLK(CLK), .CE(CE), .SCLR(SCLR), .SINE(SINE)); endmodule

When I try to synthesize xyz.v, I get the following error message:

ERROR:HDLCompilers:87 - "xyz.v" line 10 Could not find module/primitive 'sine_dds'

line 10 is "sine_dds sine_new("

I am lost, and I do not know what I am doing wrong. By the way I am using webpack 8.1

Art

xilinx_user skrev:

Coregen should also have generated a sine_dds.v file, add that to the project

-Lasse

sine_dds.v is the simulation file. From what I understand it cannot be used for sythesis - only the edif file. Besides Aurelian Lazarut already stated that I need to remove these from the working direcotyr. It would appear something else is going on.

xilinx_user skrev:

sine_dds.v has the module definition for synthesis and enclosed in translate_off/translate_on the stuff for simulation.

but if you don't want to listen ... ;)

-Lasse

work.

Sir,

Your comment: "but if you don't want to listen ... ;) " is not helpful. I originally had the .v file in the directory and it did not work. Aurelian Lazarut, who is a System Verification Engineer for Xilinx Ireland said to remove them and make sure all the edif files are in the working directory. As he works for Xilinx I am inclined to take his word.

Just for the record, the comment in the .v file is: "This file cannot be synthesized and should only be used with supported simulation tools."

I am sorry you take offense but I am losing time in getting the answer I need.

Here is the recipe that always works for me: I use the ISE GUI. When I have a CoreGen model instantiated in my Verilog, ISE leaves a place for the .xco file. In your example, your core is called sine_new, so there will be a sine_new.xco. Add that source to your project.

Among other files, CoreGen will generate sine_new.edn and sine_new.v . You should place these files in same directory as your *.ise file (the ISE project file). In general, you can't go wrong if you put every file that CoreGen creates into the directory that has your *.ise file.

I think Lasse is right here, the *.v file will act like a "blackbox placeholder" (or at least it should) I have to admit that the message in the header is misleading that this file will be used for simulation only, hence the confusion. however the "normal" flow will be to keep the *.xco file attached to the design tree, so Joe's suggestion will hold here.

Aurash

Joseph Sams> xil>

Thanks for your posting. Unfortunately I did not check back in time. I experimented quite a but and discovered the same thing.

I have alot of experience with Verilog/Xilinx, but have not used cores before. Also, I have not used the Xilinx tools for about 2 years and am getting re-used to the WEBPACK GUI.

I have another question. I am now trying to simulate the core using the ISE simulator in Webpack 8.1 I am running into the problem that the output is always 0 no what frequency I set as the 'quiescent' frequency for this core.

I know I am doing something wrong. Do you have any general observations along the lines of your reply to me? Any help with be appreciated.

Best Regards,

Art

In the core generator project options (Project -> Project Options..., then Generation tab), you can choose either Behavioral or Structural simulation files. Try them both; sometimes one doesn't work. If you do this, make sure that you connect the signals correctly when instantiating the module. Some cores have the signals in a different order depending on whether Behavioral or Structural are chosen.

Thanks. I had already tried both behavioral and structural, and neither one worked. I then did a post route simulation and that seems to work.

This simulator seems flaky, if not goofy. I am not sure I trust anything out of it.

In any event, thanks for the help.