Hallo, this may be an typical newbie-question(sorry).
My project is described in vhdl, but i have an working component in verilog i want to use within. How will i get the component in my project ?
thanks for any answer
Thomas Oehme
Hallo, this may be an typical newbie-question(sorry).
My project is described in vhdl, but i have an working component in verilog i want to use within. How will i get the component in my project ?
thanks for any answer
Thomas Oehme
In ISE 5.x, you can only use one of VHDL and Verilog at a time, using the normal "flow".
Workarounds:
2a. Rewrite your Verilog in VHDL.
2b. Rewrite your VHDL in Verilog.
Regards, Allan.
verilog
Thomas,
This depends on your tool set.
If you've got HDL->third party synthesis tool->FPGA P+R tool, this should be easy enough.
An overview is.... Instantiate a VHDL component that has the same port mapping as the VHDL component. Synthesise your VHDL and a black box is created in the EDIF file for the component.
Synthesise the verilog to create the component that'll fit in the black box (make sure you don't allow output buffers to be implelmented).
Run your P+R tool, it should then plug the edif of the component into the VHDL file.
Nial Stewart
------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design
Hi Allan:
you should be able to black box the thing, and use it as a lib
Andrew
Allan Herriman wrote:
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.