Hi all,
This question might obvious, but I cannot find any other way to instatiate signals from a top of a design for simulation purposses.
What I usually do is to add those signals as ports in each entity beginning from the bottom of the design and continuing the hierarchy until I arrive to the top. In order not to consider them in the synthesis I add "synthesis translate off/on" comments.
Here you are an example:
Imagine that I want to instantiate the internal signal of the subblock1 from the top
entity top is port( -- synthesis translate off tb_out : out std_logic; -- synthesis translate on ... ); end top;
architecture arch of top is begin
uut: subblock1 port map( -- synthesis translate_off internal => tb_out, -- synthesis translate_on ... ); end;
Then I instantiate the top in the same way from the testbench.
I know that in verilog there is another way just with something like this.
"top.subblock1.internal"
I would be glad is someone could help.
Thanks in advance,
Arkaitz.