Modelsim problem - mixed VHDL,Verilog & VHO

I'm having problems getting a simulation running. Here's the recipe...

Quartus output VHO file - contains VHDL & Verilog components. Testbench components - VHDL & Verilog components.

Note (and I *think* this is part of the problem) the VHO file contains a certain verilog modle, whilst the testbench also contains an instance of the same module, albeit with *different* parameter values.

Attempting to start the simulation under ModelSim ('vsim') loads a bunch of structures from the library, and then halts with an error that just does *not* make any sense at all!

The error is "irda_peripheral.v(155) The width (1) of VHDL port 'addr_cnt_out_2' does not match the width (5) of its Verilog connection (3rd connection)".

This error occurs in the file that contains a 2nd instance of the verilog module, and the 3rd connection is indeed a vector whose width is specified with a parameter - which incidently differs from the value for the instance inside the VHO file.

However:

• addr_cnt_out is internal to the VHO and not connected to the instance in this file at all.

• neither of the parameters specify a width of '1' for the vector.

I suspect Modelsim is getting confused between the instance in the VHO file and the instance in irda_peripheral.v and is having trouble wiring up the ports?!?

Anyone else had a similar experience?

Regards,