mixed Verilog/VHDL in ispLever 7.0 broken

G'day (o;

Just got the confirmation that ispLever 7.0 is broken for mixed Verilog/VHDL designs...my case was that a VHDL T80 Z80 CPU core module wrapped in a Verilog top file would fail with Precision unable to find work library...

Now with the patch it's running through (o;

Either contact Lattice for a fix if you have this issue or wait until end of year for ispLever 7.1 (o;

cheers rick