Counter counting on both clock edges.

This program is trying to describe something that can not be built using standard elements found inside an FPGA. Instead of trying to think in VHDL, try thinking in terms of the logic. Forget the code for a moment and figure out what logic would be generated to do what you want.

I can think of three ways to do what you want. One is to use a clock that is twice the frequency (generated in a PLL/DLL in the FPGA). Your design is a bit unusual in that you do different things on the rising and falling edges of the original clock. You will need to reference this clock to distinguish the two actions.

A second way is to use both a rising edge triggered register and a falling edge register, each a function of the other. Your logic will need to change from what you have above.

The third is to use two registers, but one logic path with a MUX in the front to switch registers as required by your function definition.

Since this is a very odd function to be implementing as part of a job, I assume it is a homework assignment. So I won't give any more details... But the main idea is to use VHDL to describe your logic...

Hi Andrew In real hardware the trick is to use a 5-stage shift register with an inverter between the output of the last stage and the input of the first stage. This should be easy to implement in VHDL. Mogens Pelle

"Andrew Rogers" skrev i en meddelelse news:4130963b$1_1@127.0.0.1...

I see this sort of answer a lot on this forum and, while I agree that we don't need to be doing someone's homework, do we really need to make this sort of statement? It's condescending and really unnecessary. If you don't want to give details, just leave them out. Let's give folks the benefit of the doubt and maybe we won't scare people away.

I -have- had to implement this sort of thing as part of a job (more than once, in fact). Another way to do this (depending on what you really need) is to construct a /10 signal, delay it by 2.5 cycles (using a neg-triggered FF) and XOR it with the undelayed version.

If the freq. of the input is high enough to allow you to use the on-chip DLL (if you're using an FPGA with one), many DLLs will do a divide-by-5.

Jake

Mogens -

That gives you a /10, not /5 (assuming you start with all 5 FFs in the same state).

But he could use your 5-stage shift register + inverter if he initialized it to "00011". Then delay the shift register output (any stage will work) 1/2 cycle and OR it with the undelayed output to create a 50% duty cycle /5 clock.

Without a 2x clock I don't think there's any way to avoid a 1/2 cycle delay someplace plus a gate. Another poster (Jake) suggested a /10 signal delayed

RJS

Thanks for all the suggestions, they are valuable ideas that I will use for similar problems.

However, I needed a divide by 2.5 in the end. A divide by 5 is simple once you have a divide by 2.5. I wrote the following code:

library IEEE; use IEEE.std_logic_1164.all; -- defines std_logic types use IEEE.std_logic_unsigned.all;

--- Divide by 2.5 counter --- entity div2p5 is port ( clk : in std_logic; q : out std_logic); end div2p5;

architecture div2p5_arch of div2p5 is signal cnt0 : std_logic_vector (2 downto 0) := "000"; signal cnt1 : std_logic_vector (2 downto 0) := "000"; signal q0 : std_logic; signal q1 : std_logic;

begin

The shift register gives you a /10 signal, right? I don't see how you generate the 50% duty cycle /5 clock from this by delaying 1/2 cycle and ORing it with undelayed output? Can you elaborate a bit?

I think Jake's suggestion makes sense, you generate a /10 clock and delay it 2.5 cycles (in the faster domain) which corresponds to 2.5/10 =

-JS-

Condescending it may be, but if I don't explain why I am leaving out details, then he won't be able to correct me if I am wrong.

Logically, this will work. But you don't need two counters, just one will do. Like another someone suggested, this algorithm generates two waveforms, each a divide by five, with a 2.5 clock phase shift. The results are ANDed to produce a waveform which is a divide by 2.5. Remove cnt0, make everything a function of cnt1 and you will get the same results.

Notice that the result will not be square (50%/50% duty cycle). I believe this is what was originally requested.

Andrew Rogers wrote:

Andrew,

To easiest way generate a 20 Mhz clock signal on the Spartan-3 starter kit from the 50 Mhz osc would be to use the DCM.

Is there any reason you have not considered that?

Shal> Thanks for all the suggestions, they are valuable ideas that I will use

initialized it

I meant to generate a /5 clock from the shift register with a 40% high duty cycle. I just realized the inverter in the feedback path needs to be removed. Anyway, take a 40% duty cycle /5 clock, delay it 1/2 cycle, and OR it with the undelayed version. You get a /5 clock with 50% duty cycle. You could also start with a 60% duty cycle /5 clock, delay it 1/2 cycle, and AND it with the undelayed version and also get a 50% duty cycle clock. Doesn't matter how you generate the clock (shift register or counter). The 1/2 cycle delay plus the gate just allows you to fix the duty cycle.

This comes up often enough, that it is in the FAQ. Although the problem is stated somewhat differently, getting a square wave from an odd division of a clock is really the same as dividing the clock by N.5 .

In your case, you want to divide the rising edges of your source clock by 2.5 (or the combination of rising and falling edges by 5).

Divide A Clock by N.5

Philip Freidin

=================== Philip Freidin snipped-for-privacy@fpga-faq.com Host for

I didn't know that there is a DCM nor what a DCM is:) Clocking a counter on the positive edge and negative edge seemed easy enough at first.

I have just started to learn VHDL and FPGA stuff, self taught so there's no course notes (or homework assignemts!). It has been a steep learning curve for me. Can anyone recommend any good and free articles to help learn VHDL for FPGA?

Thanks Andrew

If an FPGA with DDR support is the target, the DDR primitives can be instantiated directly. The ability to clock on the rising and falling edges is built-in without internal logic routing skew issues.

If a CPLD is the target, maybe a different CPLD family would be a way to go; some Xilinx CPLDs have "clock doubling" built into the flops with the posedge/negedge triggering. Not all Xilinx CPLDs have the feature.

Andrew,

DCM stands for Digital Clock Manager and has many features to generate new clocks of various frequencies and phase based on an input clock. Using the DCM would be the easiest and preferred solution to your design to generate the 20 Mhz clock.

To read more about the DCM check out the DCM Application note at:

Cheers, Shal> Shal>

I believe you are talking about IO clocking. Once the signal is captured in the IOBs, you still need a 2x clock internally.