1. Home
  2. Field-Programmable Gate Arrays
  3. Xilinx Webpack, simulate with off-chip-connected-pins? (VHDL)

Xilinx Webpack, simulate with off-chip-connected-pins? (VHDL)

Hi group, Sorry to bother you again. I am developing code for a hobby project and I need to simulate my design with some off-chip-connected-pins. For example, I generate a secondary clock on chip, output it from a pin, and feed it into another pin (dedicated clock pin). How do I simulate it? Where do I tell the simulator that the two pins are connected? I guess one possible place is the test bench vhdl source file, and another possible place is the simulator command lines where I 'force' the input pins. I googled and it seemed that I could not find a good combination of words to dig out the answer. I am reluctant to rewrite the code and connect the signals on chip, because I want to use the dedicated clock pin. Thank you.

vax, 9000

Reply to
vax, 9000
Loading thread data ...

Reply to
vax, 9000

The first, uh, second, uh, the lower question is easier to answer. Use a testbench to describe the environment the chip is working in. All of your IOs are ports at the top level, right? Instantiate the chip in the testbench module and connect the clock in/out with a signal.

If you already have a testbench, what is it doing?

As to the second, I have not done that before. I expect you can instantiate two modules (chips) in one test bench. You may not even have to do anything special. Try just adding the files for the second module to the simulator project and instantiate the second chip in the test bench.

"vax, 9000" wrote:

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX
Reply to
rickman

Err, force? Are you using a force file? Please don't do that. Write a proper VHDL testbench; google around for some examples. For the example you mention above, the code is trivial:

architecture board of bd_top is constant CLK_PRD : Time := 10 nS; signal CLK; signal CLK_FB; begin UUT: entity work.my_device port map ( CLK => CLK, FBCLK_OUT => CLK_FB, FBCLK_IN => CLK_FB );

-- Generate the clock. clk_gen: process begin loop Clk

Reply to
Duane Clark

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.