for all those who believe in ASICs....

If you don't understand the problem, you are not very likely to come up with a solution.

I'm sure Douglas Adams would agree. But you wouldn't like it.

Ever figure out what current a wafer full of die would draw? Now for the fun part. How to get all that current to all the die without too much voltage drop? Oh, and what if one die is in latchup?

I thought you were not going to use an ATE.

As long as test coverage is way less than 50%, sure.

-- Phil Hays

Quite true.

You probably will not like the contradiction that it poses either:

a) Experienced team A works diligently, ending in a heroic failure

b) Team B offers regular help, which is turned down

c) after the failure is complete, Team B completes the project quickly.

Should Team B have accepted the failure as hard fact that the problem had no viable solution, and also failed by failing to try? (IE learning from Team A's failure)

In 30 years of being self employed I've made about 20% of my income from taking over failed projects with a low bid no risk flat fee proposals to management ... no delivery, no payment. All I have at risk is my time and my reputation to always succeed on those projects. Several of those projects were taken from experienced teams that I offered friendly help on a regular basis, and was turned down. Others I took after one or more other companies failed to deliver what the client needed, often with sharp adivice that I would be doomed to repeating the cycle.

yep ... and did you notice the part of the proposal about using on wafer power control for each die?

Did you notice the part of the proposal about using ATE for screening dangrous defects, like shorted power nets?

You have already given up if you think that. The explict idea behind defect managment is functional issolation by designing for 100% test coverage at some level of detail. Either a route, FF, LUT, buffer, or other resource fails testing, or is presumed operational, and to be screened if necessary by using redundant logic in the system level design initially.

I suspect that this will be an itterative process of incremental refinement over a long period of time, maybe at first only saving

40-60% of the reject yield, and possibly progressing to nearly all. I suspect one of the most important parts of the process will be design refinements to prevent/issolate the failure impacts on future designs, increasing both the primary and secondary yields in the long term.

One interesting form of "success" includes not reaching the entire objective, but leaving a carefully documented road map of the challenges, assumptions, and proposed solutions along the way so that those that follow have a better defined path to chip away at.

Now, I don't know how much of Xilinx's yield is scrap today, or would be scrap at the end of 6 months, a year or two years. I do suspect the number will steadily decrease using design for defect management strategies.

I do know the "cost" to Xilinx to sell scrap die and packaged product is pretty low, if it comes with a long term partnership to provide engineering input to increase yields for both zero defect, and managed defect segments. The long term promise of such a program is for each to act in good faith to increase revenues for both partners as the process matures.

I believe that I can create products which are defect aware using the largest Xilinx parts, that presumably also have the largest percentage of rejects. I'm willing to invest the engineering into developing a recovery process, if Xilinx is willing to provide scrap material, and include in that partnership an agreement to share data and design suggestions to improve yeilds. As the recovery process becomes profitable, there is certainly incentives on both parties part to share that windfall. That's a pretty low risk deal for Xilinx if they are crushing scrap in die and packaged form today.

I'm willing to consider the same for other FPGA vendors as well.

Sounds simple - become an EasyPath customer!

You can make your own bit streams ( IIRC, two are allowed ? ), and thus get die that are in a 'possibly faulty, but partially proven' bin, and expand from there.....

-jg

It's the NRE and volume commitment that are the real OUCH.

I'm glad that the $5-10M is pocket change for your business.

Hmmm ... I thought I saw a statement there was a 10,000 min for the program, which I don't see any more .... might not be as big a hit.

John,

I'm not saying your ideas won't work, I am saying that you have a very large task ahead of you, perhaps larger than you realize. I'd like to see you pull it off, as doing so would mean that you've solved a number of vexing problems that have plagued the RC community for a long time. A solution to many of those problems would also greatly benefit the designers of static designs as well.

So far, however, your posts have pretty much focused on whining about what you can't get rather than on solutions to the known problems. There is a tremendous amount of FPGA experience and knowledge among people on this newsgroup. I believe many of us have tried to point out the pitfalls (that many of us have already encountered) so that you might have an easier time navigating the field. Your responses so far have mostly been whining about what you can't get rather than looking at ways to get around those obstacles within the framework of what is available. Posting it here and not listening to the advice the seasoned veterans here have offered only serves to sour people on your ideas. If you truely feel you've discovered a route to success that others who've been playing in this field for over a decade have not seen, then it would make sense for you to first get patent protection for your ideas, and then go into Xilinx and other FPGA vendors and negotiate with them for what you want. If you have a convincing story, I suspect they'd be asking you what you need rather than the other way around. If you can solve the fast PAR issues, for example, you could probably fund your development with the proceeds from the FPGA companies lining up at your door to buy rights to your PAR algorithms.

When I referred to the system, I am not just talking about the FPGA boards. That's the easy part. I am referring to the implementation tools, libraries, user interfaces etc. Many of the major pieces you need are still a long way from being developed enough to be usable in a general purpose RC system such as you have described.

The responses so far have been far from advise, they have been the stock answer that it's been tried before and fails. Advise to fail by failing to try.

Advise is suggestions on how to move past prior failures, and get past the limitations of the existing tools.

and also this one :

Here, AMIS claim 3000+ (rolling sum) FPGA->ASIC conversions.

Atmel also have a ULC conversion program.

-jg

All,

For "burger counts":

(July 7, 2003) (June 17, 2004) (September 21, 2004) (December 27, 2004) (December 20, 2005) (February 28, 2006)

And now, AMI...

AMIS:

FY 2001 2002 2003 2004 2005 $$ 326M 345M 454M 517M 504M SA 0 0 96.7M 119M 110.4M

So, let me get this right, in 20 years, they have converted 3,000 FPGA designs to ASICs.

And, in the last three years they have redefined part of their business segment, and called it 'Structured ASICs', and revenues were down this year from last.

Anyway you cut it, it doesn't look pretty.

The gross margins also look rough (anyone out there ever worked for a company with ~ 40% GM? not fun at all...bring your own hand towels time).

That makes structures ASICs flat to down for 2004 to 2005 for AMI.

This is similar to MacDonalds giving the bizillionth customer who orders a prize -- it tells you nothing, other than someone got lucky. Now a history of increasing 'burger counts', that at least tells you something.

In this case, the 3,000th conversion customer got lucky: they got a working part!

In all fairness, more power to AMI: they have been in this business for a very long time, and they obviously know how to make money in it.

The other link for the FPGA journal is much more interesting (Kevin is pretty sharp!): (from his article)

(when asked 'is structured dead...')

"Our answer to these questions is an emphatic "no." The reasons behind LSI's strategy shift are complex and somewhat company-specific. No company can do everything at once and do it well, and smart executives know how and when to focus their company's energies on the projects that will bring the most return and growth and that capitalize on the organization's unique strengths. LSI had good momentum and competence in the storage and consumer markets, and those made sense as a place to focus the company's remaining resources in a difficult business situation."

I call this the 'apologia' as it is the restatement of the company line why they left the business (even though they were #1). LSI found the business did not fit. It happens.

"The part of the situation that isn't company specific is the orthogonal trend toward domain-specific optimization of silicon platforms. This specialization can be seen across industries and across silicon technologies. With the exception of full-blown ASIC, every customizable silicon technology makes some serious technical compromises. For FPGAs, these compromises are obvious in the LUT fabric which gives away an order of magnitude or so in speed, density, and power consumption for the privilege of reprogrammability. In structured ASIC and in non-volatile FPGA technologies like antifuse, the configurable fabric penalty is smaller, but still significant. Every vendor's solution to this problem is the same ? create ASIC-like hard IP blocks for critical functions."

Here Kevin answers the reasons why (that he artfully dodged earlier), without saying that LSI realized it was failing. He basically says: this business is really tough! You never have the right mix of IP, etc. Back to Kevin:

"Hard IP can take large, performance-critical hardware, like multipliers, memory, and high-speed I/O standards, and implement them much more efficiently than a designer attempting to put that same capability in the programmable or customizable part. This gain comes at a cost, however. Every customer that doesn't use a particular function that is hard-wired on the chip is essentially paying for wasted silicon. The juggling act for semiconductor companies, therefore, is to decide which functions (and how many) should be hardened in order to give the best mix of performance and cost optimization. For example, if your customers are doing high-speed digital signal processing (DSP), it probably pays to put a number of hard-wired multipliers on your chip. Even then, however, the question of "how many" poses a challenge. Do you need ten? A hundred? A thousand? The particular application area determines the answer."

So, the 'trick' is to know the customer, and know what 'works'. The way to tell if a company knows these things is to keep track of their financials.

Austin

Hmmm....

Austin's earlier claims...

12 companies in that year. >LSI had the largest share of that, at 35M$. Everyone one else had a smaller chunk than 35M$.

If I read your table above correctly, you have AMIS at $110.4M SA in

2005, but just a few "Austin-Arm-Waves" ago, you had LSI as the Largest player, at $35M ?!

Still, I guess it makes for rather less dramatic arm-waving, if it is not _actually_ the largest player that has just exited... ?

Shame to let the numbers get in the way of a good spin :)

-jg

JG,

Who ya going to believe?

AMIS finacial post on their webpage (to the federal governement)?

Or some silly market research company that they try get people to buy?

I noticed this too.

So, is AMIS overstating their Structured ASIC wins to their stockholders and the governement? Shades of Enron?

Or is Isuppli using a different definition? Or just doesn't know anything?

If this is about < 35M$ vs ~104M$, then I rest my case: structured ASIC is dying...or already dead.

What the investors thought they would be seeing is another multi billion dollar market by now. And growth.

These numbers (pick any) are just pitiful.

Austin

"Paying for wasted silicon"... isn't that what FPGAs are all about, wasting a bunch of silicon so that you get the benefit of the small portion that you use? In fact, isn't that the crux of the philosophy of Easypath, not testing all the unused, wasted silicon?

Once a Xilinx FAE was trying to explain the economics of FPGAs (logic vs. routing) and expressed the fact that the routing dominates the die area by saying, "We sell you the routing and give you the logic for free". That was supposed to mean that I should not be concerned that I could not use all the logic (wasted silicon) because of routing congestion.

Ironic that Xilinx would hold Kevin's feet to the fire for understanding wasted silicon when Xilinx's entire business model is founded on "wasted silicon".

;^)

Rick,

I don't understand your comment.

Of course we have "wasted" silicon. That is the basis of the whole FPGA architecture. It is also the basis for our success:

Knowing what to put in the chip, and what not to put in the chip.

Knowing what to hardern, and what not to harden.

Making bizillions of the same chip to get economies of scale so the "wasted" silicon doesn't cost the customer what it would if it was an ASIC.

It is more of an issue if you are a structured ASIC (back to Kevin... he gets it). If you are a structured ASIC, you are attempting to be a platform for a wide range of designs, with two or three masks for all customization.

You need: MGTs, BRAMs, DSPs, PLLs/DLLs, EMACs, PCIe, (and the list goes on, and on, and on).

As an ASIC this is really expensive, if no one uses even one of these cells. That is serious area we are talking about here. Doubling the area with wasted stuff.

For an FPGA, the routing alone used up area (along with the memory cells to control it) so adding a whole bunch of hardened IP just made the FPGA more of a bargian, not less. Adding less than 5% area with stuff that may, or may not get used, but is used far more often than interconnect!

Aust> Aust>