I have implemented a 8-bit synchronous counter by VHDL. The result is that the LED display show continuously running the count from 0 to F(in Hex). Now, I need to change the result which the LED display can count from 0 to 9 only. How can I change in the VHDL code? Can anyone answer me? Thanks a lot!! The following VHDL code are about 8-bit synchronous counter: Library IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_unsigned.all;
ENTITY counter_eg IS PORT( PB1, clk_25MHz : IN std_logic; led0, led1, led2, led3, led4, led5, led6 : OUT std_logic); END counter_eg;
ARCHITECTURE c OF counter_eg IS
COMPONENT counter PORT( Clock, Reset : IN std_logic; count : OUT std_logic_vector(3 DOWNTO 0));
END COMPONENT;
COMPONENT dec_7seg PORT( hex_digit : IN std_logic_vector(3 DOWNTO 0); segment_a, segment_b, segment_c, segment_d, segment_e, segment_f, segment_g : OUT std_logic); END COMPONENT;
COMPONENT clk_div PORT( clock_25MHz : IN std_logic; clock_1MHz : OUT std_logic; clock_100KHz : OUT std_logic; clock_10KHz : OUT std_logic; clock_1KHz : OUT std_logic; clock_100Hz : OUT std_logic; clock_10Hz : OUT std_logic; clock_1Hz : OUT std_logic); END COMPONENT;
SIGNAL count : std_logic_vector(3 DOWNTO 0); SIGNAL clk_1KHz : std_logic; BEGIN c0: clk_div port map (clock_25MHz=> clk_25MHz, clock_1KHz=>clk_1KHz); c1: counter port map (clock=>clk_1KHz, reset=>PB1, count=> count); c2: dec_7seg port map (count, led0, led1, led2, led3, led4, led5, led6); END c;