for all those who believe in ASICs....

Ok, if handles and other names represent a sense of shame, are you suggesting that the founders of Xilinx were ashamed to use their own names, as Hewlett and Packard, Ford, and many other great business do?

Should we start riddiculing your employer for this too?

I think not ... the only shame is that Xilinx is allowing you to dirty their name.

John Bass

I understand a lot of the testing for Virtex FPGA's is built on using the reconfigurable interfaces to load dynamic tests. I remember reading about that in the past, plus saw a 3rd party selling such tests to customers for in field verfication.

As soon as the chip becomes "hard" with the routing frozen, that quickly goes away as an option, so that customer test vectors must be written based for full coverage of the design again (just as with ASICs). And good coverage BIST becomes difficult again.

This seems to me that it increases testing complexity and NRE, not reduce it. That it then requires expensive testers for all testing, rather than using generic loadable BIST configurations which can be managed by less expensive test interfaces.

Still pondering this question after reading a bit more from the Xilinx site. Two issues are still nagging at me. Since the full fpga isn't tested, that presumably means that sections of any particular device purchased under the easypath program may have serious problems that are not screened for, which would prevent the customer from using generic

3rd party reconfigurable self tests for that FPGA device which use resources outside of the two qualified "hard" bitstreams, since the generic tests may fail in unpredicable ways. This means that the customer still has an application specific test development expense, similar to that for an ASIC, but with limited ability to design for test as they would with an ASIC. This seams to complicate the post board attach and RMA board level testing, rather than make it easier than an ASIC. Ditto for field diagnostics.

The Xilinx statements are that easypath devices are identically the same fpga. Then what stops a large customer from purchasing only easypath qualified devices in very large quanties and use those that pass a full device test as replacements for applications that need full reconfigurable FPGA features, and those that don't, in the application that they were originally screened for? With up to 80% discounts this seems an attractive way to play the yield odds for very discounted full function devices, with customer testing/binning of the rejects to the applications they submitted the bitstreams for.

Assuming Xilinx's yields are not totally tanked, it seems that if they are willing to sell minimally tested devices for the best possible prices, then there is a market for 3rd parties to do the testing and screening, leveraging the volumes and margins over several products/customers.

I'm thinking here that many reconfigurable computing applications could be designed around qualified device section failures with mimimal effort using dynamic linking (Place and route). I would not have a problem at all building large systems that included dynamic defect sparing, much we do with drive arrays, to get the best possible price for high end systems, as well as consumer grade home/hobby systems.

If Xilinx is offering 80% discounts for minimally tested devices, what discounts can I get for ones which are mostly functional, but with a few known failures to map out? Maybe up to 20-30% of the device? These would be rejected and scrapped as failures if I understand the firm no-binning/selection of failures statements. So it seems they could also have even better discounts as they are "free" profits from scrap materials.

Only if you consider margin as a percentage of sales. That may be standard practice, but the implication may not immediately be clear. Under your above explanation, you would be making only about half as much money per chip with easypath devices as with regular devices, and it seems that your willingness to do that is a source of a fair chunk of the savings.

Isn't that obvious? If the product costs us half as much to make (higher yield), then we can sell it for half the price, and make the same perent margin. Margin is always expressed as a percentage. There is no other way. I really thought that everybody would understand that... Peter Alfke

John,

Stop playing the fool.

If one memory bit is bad, out of 20 million, then that FPGA can not be used for the general public.

But if you don't use that one bit in your patern, then that chip is perfect for you.

One bit.

That is all we are talking about here. That is EasyPath(tm).

One bit.

The majority of faults that prevent a FPGA from being perfectly good, are just that, one fault, one bit.

One path missing (metal is open).

One bit that won't write.

One bit that won't read.

One LUT bit that can't be set.

One IO standard that isn't there.

Maybe you should go take a course on semiconductor manufacturing? Go actually learn something?

Since we can't educate you, and you are unwilling to listen to us, maybe you should go talk to someone you trust, and will listen to?

Austin

Wafer costs for leading edge processes were way over $100 in the

1980's when I was working in the semiconductor manufacturing business. A quick google gets me:

Making leading edge chips is not cheap.

-- Phil Hays

If Ford decided to dump perfectly good Lincon's at 80% quoting they were saving QC costs for the occasional scratch or miss alighed seat frame, or what ever ... defectives ... we would laugh our heads off and realize that it was a marketing ploy to dump product below market. If they were laughing that they were driving a competitor out of business by that businesss tactic at the same time we would call it dumping, anti competitive, and a lot more ...

If any of the Asians were dumping Silicon product in the US with the weak claim some are slightly flawed, the dumping howl wouldn't stop...

Choosing NOT to test on dies that have statistically good yields, in order to dump product below Structured ASIC's pricing, and then start this thread howling about driving them out of business?

So, if you want to be a Tin Aus ... by calling me a fool and raising this to very personal attacks ... then lets get with it.

The foolish part here is gutting competitors with absolute glee, and then getting upset when someone questions that. I don't buy dumping X percent of your statisicly good known chips below market is a wise business decision, any more than I would buy Ford dumping Lincons to drive a competitor out of business by "saving QC costs". That die is expensive, has real value, particularly the percentage of them that are statistically perfect.

There are people that will buy hard drives with errors, and map them out ... practically the entire industry.

There are people that will buy FPGA's with a few bad bits too ... at significant value, and map them out too. Or test, screen, and bin them as the easy path program, and not use them for certain designs that are affected, or roll a second bit stream to work on a bin selected group with mapped failures (as easypath program suggests).

So you want to call me a fool .....

I hope there is someone in your company that has a LOT more sense ....

We all know that ... I choose a nice round number to do math with ... that's all ...

The whole point is that perfectly good FPGA's aren't cheap ... and to dump them without testing them at 80% off, is dumping high value product below it's full value.

"dumping" is selling something below cost, not taking a lower margin than premium, "perfect" products.

He doesn't have to call you anything - you make it rather obvious.

...as I hope you have access to professionals with more sense to help smooth out your rough edges.

By their own statements, they do not screen the good parts first, so depending on the wafer yield, a reasonable percentage of those are parts ARE premium, "perfect" products being sold as low as 20% of the normal price.

Again, selling below MSRP is *not* dumping!

Dumping is selling parts below cost. We're talking negative margin here.

When xilinx writes a PO for 100k devices _from_the_fab_ at $N per device, it's dumping if they sell that device for less than $N.

Do the math ... if the typical product margin is above 60%, and the typical costs of sales is some 36.6% of revenue, then dumping at 80% discount, is recovering 20%, and well below 36.6% the typical cost. When some percentage of those sales are statistically perfect yield parts, that they decided not to screen I'm pretty sure any sane person would agree that perfect parts sold at half normal "cost" is just that. If the yield cleans up to 50-80% good parts, then program is clearly dumping.

Now, if the offical word is that they test every part completely, and pull the perfect parts then you would be correct. The whole program would make sense if they were selling known rejects. In fact, there are a number of people that would probably stand in line for parts with a one bit error as Austin says. Bin them into sixteen subquadrants and people would eagerly purchase them in volume avoiding that 1/16th of the chip with par for entire production runs.

We've heard a lot of whining about dropping non-profitable support ... how long is a program going to last that ships as many perfect parts as very slightly flawed parts?

if they were selling bare die, then $N would be correct.

They are however selling packaged and tested parts, so all standard burdens, labor, buildings, IP, etc apply to the cost -- not just die cost from the fab.

No, I don't think it was at all obvious that Xilinx would be willing to sell its IP for half price.

When the incremental sales are significant for a small percentage of Xilinx customers, this program should have a long, happy existence.

Oh, and your flawless understanding of market dynamics has convinced me that Xilinx is a bad investment. Yeah.

The Emperor's New Clothes ... even without clothes, he's still the Emperor.

I assume that last straw of a jab, means that you decided that an 80% discount is actually below cost.

Can I take my Devils Advocate hat off now?

Conversely, what really happens to the devices not originally allocated to easypath which have single errors. Are they crushed and returned to the sandbox? Or do they get a second chance at proving their worth, on the easypath tester?

John,

How much is Altera paying you?

Austin