for all those who believe in ASICs....

John,

Interesting opinions.

Of course, I disagree that ASICs have any rosy future at all, and I also feel that your conclusion that whoever controls the foundry controls the technology is also quite bizarre.

How many patents does Xilinx have?

How many are due to expire?

How many that are due to expire matter? (All it takes is one of the most recent ones to be a barrier to entry...for the next 20 years).

How many lines of code do you need to support your FPGA design (in the tools)?

How many hotline engineers does it take to support FPGAs?

How do you train and support the distributors, FAEs and customers in a new technology from a new vendor?

How much circuit design for FPGAs is done outside the US? Outside silicon valley? How much software for CAD tool support of FPGAs is done elsewhere? Where are the patents being filed?

Xilinx doesn't just excell in one area, we excell in as many areas as possible. Each by itself is a huge barrier to entry.

Only getting tougher to compete.

And, we don't stand still. Did you see the 65nm FPGA announcement last week?

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And, have you heard anything about that 65nm ASIC process being ready for anyone, anywhere? For anything? Other than it is too much money, and too much power? (with no proven IP)

Ouch. Where is all that new cool 65nm IP, and stuff for that next killer application? MGTs, MACs, DSP, PPC, etc.

Oh, Xilinx has it in their FPGA.

Austin

Reply to
Austin Lesea
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Jim,

I beg to differ. In terms of power, resistance to neutron SEUs, and signal integrity, our silicon has significant advantages.

One not so small feature: we have 90nm triple oxide.

The process was developed for us, at our request, by two foundries.

Oh, and we have it for 65nm, too.

Wake up and smell the coffee. We asked for a process, and we had more than one foundry eager to supply it.

That sounds to me like a revolution in the fabless model. Instead of "give me your masks and I'll give you some chips" we have a working partnership and cooperation in developing a new process unique to our industry.

Austin

Reply to
Austin Lesea

All it takes is demonstrated prior art to avoid it as well, plus some litigation to avoid the challenges. By 1989 what was published regarding FPGAs, and the devices that were in production at that time, provide an architectural wealth for producing patent free comodity FPGA devices, which scaled to current processes, would make a strong competitor for main stream FPGAs. The market for advanced FPGAs would at that time not be nearly as high margin with the cash cows slaughtered, and the competition would become stiff.

Reply to
fpga_toys

A more intersting discussion for me is the best path for converting expensive high end FPGA designs into ASICs. I viewed rapidchip as one of these paths- so what's left? Is this even a big business?

Xilinx: easypath - lower cost but no faster.

Altera: hardcopy-II - these are structured ASICs. They look appealing, but I did not get the impression that there were many conversions (at least as of a year ago).

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Reply to
Joseph H Allen

Volumes and TTM (time to market) will dictate the path you take, either ASIC or structure ASIC. And sometimes they both can work for you. We have a recent product with projected numbers that make an ASIC the best candidate, lowest UMC. The downside is that the ASIC has a long schedule; so long that we would miss launch: missing the market with a product can cost a company big $$. The answer, launch with a structure ASIC (Altera HC) and roll in the full ASIC later in production. Yes, you get nailed with 2 NRE's, but if your numbers are high enough (as they are in our case) the business case can make sense.

In our case the ASIC was a little less than half the cost of the Structured ASIC. Altera's HC also can afford you a pin compatible footprint such that you can plop an FPGA down on your production board if you wanted to do further development.

Reply to
Rob

NEC has a structured ASIC family (like the ISSP90).

Petter

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Reply to
Petter Gustad

snipping

I notice on the job listings for Xilinx that most all of the good stuff is in the US CA,CO etc, but on that other companies website, they seemed to have half their VLSI design reqs in Malaysia last time I looked, perhaps cost cutting or something.

John Jakson

Reply to
JJ

Xilinx have a circuit design group in Ireland also.

Alan

Reply to
Alan Myler

Pity; I'm doing a RapidChip at the moment. I guess they got their business model wrong, but there are still half-a-dozen other people in the market, and I'd be surprised if we don't see more.

On the RapidChip, it was (then) a no-brainer: 110nm, (much) bigger than any 'real' FPGA, much better performance, good unit price, and the total NRE+tools cost was equivalent to the cost of about 50 or 60 of the same-size (but slower) FPGA equivalent that I was quoted for.

I don't know about the others, but LSI wasn't disguising this as anything other than ASIC design. ASIC design is not actually that different from (good) FPGA design.

Evan

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Reply to
Evan Lavelle

It depends what you mean by ASIC, of course; I can just about imagine a future in which a fair number of the functions we nowadays associate with chipsets are performed in an FPGA (indeed, the Cray XD1's network-chip to processor-chip logic is a large Xilinx chip).

I can even nearly imagine one where FPGAs have taken over the job of graphics processors; current graphics processors are pretty much a large grid of floating-point units with interconnect.

I don't see one in which the functions we nowadays associate with CPUs in things we think of as computers happen in FPGA: the incentive for greater performance is enough to make it worth doing actual circuit design, and an FPGA containing a credible CPU as a functional block is not going to be competitive with that CPU implemented without the surrounding FPGA.

Though this may mean that you end up with an ecosystem containing some FPGA vendors, Intel, and possibly a couple of other CPU manufacturers (IBM, AMD?).

I think there will be a role for ASICs when you want to move data around at enormous rates in truly-commodity applications: an eight-port gigabit ethernet switch ASIC, essentially eight gigabit transceivers bought from an IP firm and pasted around the edge of a small amount of routing logic, is in volume going to be cheaper than an FPGA with lots of logic in the middle and eight transceivers around the edge. OK, CISCO's bigger routers are sold at margins where you can afford to buy Virtex4 chips just for the transceivers, but there's a much larger, more price-sensitive market in the home.

As I'm sure you know, Intel has shipped several million 65nm ASICs in the last few months.

Tom

Reply to
Thomas Womack

I think Austin most likely meant "is anyone selling a 65nm cell-based ASIC design flow", rather than "is anyone shipping a product based on a full-custom 65nm process".

As you pointed out, it makes sense for Intel to do deep-submicron design. But for most people, it's surely far more economical to let (e.g.) Xilinx solve that particular very hard problem for you. After all, you already have your own solution space to worry about - graphics, or DSP, or wireless, or whatever - why focus on anything else?

Cheers,

-Ben-

Reply to
Ben Jones

Hi Joseph,

"Altera: hardcopy-II - these are structured ASICs. They look appealing, but I did not get the impression that there were many conversions (at least as of a year ago)."

We have many customers lined up to use HardCopy II, and have have had a significant number of conversions in the original HardCopy devices; one example is TI's DLP chipset (yes, I'm talking about those fancy HDTVs). HardCopy II is particularly exciting because it uses a very efficient fine-grained logic fabric and provides a choice of migration devices allowing greater cost reductions than previous members of the family. HardCopy II also provides a significant speed-up over the equivalent Stratix II FPGA devices and cuts power consumption in half.

I don't know why LSI is exiting this market. But there are a few advantages Altera has offering a structured ASIC over pure-play structured ASIC vendors. First, we can leverage existing sales channels and contacts from our FPGA products; selling a structured ASIC is a lot more like selling an FPGA than it is selling a standard-cell ASIC product.

Second, our customers can prototype immediately in an FPGA, and can sell that prototype for as long as it takes them to finalize their design and commit to the HardCopy II device. They can wait for their product to take-off before migrating to HardCopy II for a cost-reduction, or they can move immediately into HardCopy II in order to attain speed, power and cost advantages.

Third, and certainly not last, we can leverage our software and intellectual property from our FPGAs. We put a full-fledged CAD suite (Quartus II) on the customer's desktop, allowing them to design, iterate, and close timing before handing off the design to us. The software is easy-to-use (especially by ASIC standards), giving push-button RTL-to-Silicon results. In addition, we have a large library of Altera and 3rd-party intellectual soft-IP that customers can use in their designs that have been tested in numerous FPGA designs. And HardCopy II devices incorporate much of the hard-IP from our FPGA devices, such as PLLs, I/Os and RAMs, and work the same way as the Stratix II FPGA.

Regards,

Paul Leventis Altera Corp.

Reply to
paul.leventis

Hi Jim,

Actually, there is a lot of R&D spent on the logic and routing architectures of FPGAs (never mind other integrated IP) that has a large influence on the speed of the resulting chip. And then there's the software... what is the difference between transistors getting faster by 5% and an algorithm enhancement in the placer (for example) that gives 5%? From a user's perspective, nothing.

Lets pretend for a moment that Altera & Xilinx high-end FPGAs are the same speed (based on our experiments, Stratix II has a considerable advantage, but anyway...). The reason for this is not because its easy to make good FPGAs, but because both Altera and Xilinx employee a large number of smart, experienced FPGA architects, IC Designers, and Software engineers that are capable of wringing out every drop of performance they can. These innovations result in improved performance from one generation to the next, more than would have been possible by process technology alone.

Sure, process technology helps, but even that isn't as free as it used to be -- it takes a lot more effort these days to simultaneously gain speed, reduce area and keep power under control when moving to new processes.

Regards,

Paul Leventis Altera Corp.

Reply to
Paul Leventis

Who bears the cost, if the hardcopy migrate fails ?

How many of the Hardcopy II have not worked after the move to ASIC, and needed a re-spin ?

-jg

Reply to
Jim Granville

Yes, but my statement still stands. The devices nett performances ( SW and Silicon combined ) are actually quite similar - there is not a

4:1 edge, as one could expect from a 15% improvement every year, for a decade.

Same with Intel and AMD. Years of effort, and still very similar results.

Instead, the marketing depts have to resort to selective spin, to try and make each iteration sound larger than it really is.

-jg

Reply to
Jim Granville

I don't have any stats on re-spins and failures (I'm not in that group). But HardCopy II is an ASIC. If the customer makes a mistake in the design and discovers it after tape-out, they have to pay for it. It costs Altera engineering resources to perform the migration, and costs us for the few custom masks needed, and for the production run. We are not a charity :-)

The beauty of HardCopy is that we've had quite a few instances of customers who sent us their "final" design, only to let us know moments before tape-out that they'd discovered another bug in their FPGA prototype system. Do these customers get charged for a partial tape-out (we didn't make the masks, but we did do some engineering work)? I don't know. But I'm sure it cost the customer a heck of a lot less than a full ASIC (or structured-ASIC) run + 3 months to market that it would have cost them without the ability to prototype in advance.

Regards,

Paul Leventis Altera Corp.

Reply to
Paul Leventis

The Intel/AMD example is a good one. Sometimes one vendor has the advantage over the other (AMD has one right now). But overall, the two companies basically innovate at a similar rate. Does this mean they are only reaping the benefits of process technology? Does this mean their claims of performance improvements due to innovation are not valid? I'd argue no (well, lets ignore NetBurst for a moment ;-)).

All I'm saying is that the average rate of performance increase in FPGAs is much greater than that of the underlying process technology (which I believe was your initial statement). I would not expect a 4:1 advantage from one FPGA vendor to the next; both vendors are innovating at a similar rate per year, with some jumps here and there. I'd argue this with a simple existance proof -- if one company was doing so badly, they would disappear from the market. This has happened in the CPU market and in the FPGA market, where companies that fall behind in innovation fail and disappear.

Even the Xilinx vs. Altera epic battle has not been a neck-and-neck race. Xilinx was getting trounced by Altera back in the Flex10K days

-- but a combination of innovation and competitor mis-execution got them back into things. Similarly, Altera was starting to fall behind until Stratix & Cyclone came out.

If it were easy to make a cost, power and speed competitive FPGA, I'm sure there would be other players in our market (given the profit margins). But it isn't, which is good -- it keeps my job exciting.

Regards,

Paul Leventis Altera Corp.

Reply to
Paul Leventis

Paul,

Nice post. Not often we agree.

Overall, I am very pleased with the thread.

LSI Logic was the dominant structured ASIC player with 42M$ in 2005 (numbers from ISuppli). There are 10 other vendors left now in this space, for a total market of 155M$ in 2005 (same source).

Out of those 10 vendors, Toshiba announced in June that "there is no money in this market" (from a EE Times article, 6/5/2005). Is this a case of the "emperor having no clothes?" Or just no money in this business?

5 of those vendors offer 90nm, the rest all have older technologies, some as old as .18 micron.

Two vendors that used to be in that business also left in the last year.

If Altera gets some of that 42M$ that LSI has dropped (although LSI will convert anyone who desires to the standard cell flow), then that will be good for Altera. Good for the other 9 players, too.

Generally, the structured ASIC venbdors have as many mask sets as they have customers, which means that the vendors have not saved a penny, and in fact are losing money.

So, it is a great deal for a customer who wants a cheaper ASIC, but how long will companies stay in the business of losing money?

When the dominant (that means #1) supplier of structured ASICs calls it quits, that is not a sign of a healty market (IMHO).

So, while Altera runs off to do (structured) ASICs, we will instead continue to believe that programmable devices are the future, and continue to spend all of our effort (as in R&D $) on innovation in that field.

Austin

Reply to
Austin Lesea

Austin, Paul -

Why no mention of EasyPath or HardCopy? Where do those flows fit into the FPGA vs. structured ASIC battle? Can you guys share any numbers for your respective "ASIC conversion" programs? As in how many design conversions per year, trends up or down over the last few years, profit margins vs. your FPGA business, cost for an EasyPath or HardCopy part vs. an equivalent structured ASIC part from one of the nine remaining vendors? Are these programs viable and will they continue? I've seen both of you guys bail from similar programs in the past.

Good thread.

Rob

Reply to
RobJ

Rob,

Easypath is not a structured ASIC, it is an FPGA. Identical in every way to what the customer is already using. Except that we haven't tested the bits they don't use.

As for "success" of Easypath, it requires no design, no software, and no support. No R&D. Completely different business model.

So just one customer for Easypath is direct $ to the bottom line.

Obviously, we have more than one customer, yet I am not able to give you the exact number (as we consider it proprietary).

I do not consider Easypath as a competitor to ASICs (structured or otherwise), but as a cost lowering alternative for FPGA customers who no longer need to reconfigure their product. In effect, this is a new segment of an existing market.

Would these customers go to an ASIC if Easypath was not an option? I really don't know. I suspect not. I suspect they would just move on to the next product, and either end the life of the one, or accept reduced profits and reduced sales.

I know that Easypath is positioned as an alternative to Altera's HardCopy, but I disagree: Easypath is just that - easy. HardCopy is just that - hard.

One is buying exactly the same silicon for a lower price, and moving on.

The other is converting from a FPGA prototype of your design, to an ASIC, with all of those real risks (and I have heard of real cases of failure to converge from customers doing just that) and time to market issues.

We did have a program for cost reduction, and hardening the FPGA design. It was called Hardwire. We had Hardwire 1, 2, 3... All we learned from this was the ASIC business is not our business (it is totally different business). And, we also learned that it is incredibly hard to make any money. Lots of competitors, many that are very hungry, and will drop the prices to take business beyond sanity.

The structured ASIC shell and pea game is just that. Some of our hardwire products were just vias to short out memory cells, so the "conversion" was only a couple of masks, and costs were supposed to be incrediby low. Not. The story was good, but the reality was horrible: it didn't work the way it was supposed to (sound familar?). We eventually ended up with a standard cell ASIC flow after a gate array flow. Guess what? Didn't matter what the flow, it was still the ASIC business. You still did an incredible amount of work once, for one customer, with no guarantee of success, with no future, and no reuse of anything for the next technology node.

With a real chance of failure. If the customer makes a mistake, we both fail.

I like the model for FPGAs: if the customer makes a mistake, they fix it, and move on. Meanwhile we are succeeding with all of the other customers. They will succeed, too.

If you will, we already have "been there, done that" and decided that we should stick with the customers, markets, business and business models that have made us the success we are today.

Let those nine companies circle the drain, the plug has been pulled.

Austin

Reply to
Austin Lesea

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