Delay in Verilog for Asics design which is synthesizable

Can you use a chain of flip-flops, or some other digitally quantized thing? If not, then the answer is that you'll have to engage in analog trickery; VCC servoed inverter chains or the like.

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Rob Gaddi, Highland Technology -- www.highlandtechnology.com
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First answer is just "NO". There is no way to do it, and there should be no need for it on a proper synchronous design. Using combinatorical delays is a really bad solution because it will be dependant on fpga batch, environment (temperature, voltages), and internal routing. You simply have very low guarantee that it will work on your next design, or even tomorrow, when the wind has turned.

Second answer is "maybe".. if you have a DLL and a known clock available, you may use the DLL's delay taps to generate it, but there should still be no need for it.

Maybe you should explain why you need it? If its for i/o timing adjustments of very few signals, I would recommend external passive delay lines, like

. As you see, they are not cheap. Also you need to be extra careful with impedance matching on your pcb.

I have used with success a similar (but smd from Murata) 1.0ns delay on the clock to get timing right for an external DVI transmitter chip.

In article ,

1 ns is only 6 inches of routing.

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True, but to be honest I didnt know the delay when pcb routing so I added this general delay device and experimented.. (The chips datasheet does not come with timing(!), only a reference to the SDVO (Intel) spec wich is not public. Also, this carries up to 165Mhz clk, so I didn't want antenna problems. At that specific design I didnt have a DLL available to tune it either.

Correction.. If any interest, it was the DVO spec, not SDVO.. And the chip was the Sii 1178 in low swing mode.

no=20

But if you really need to...

Instantiate a chain of buffers or delay cells. You wont be able to get a fi= xed delay of 10ns, but you maybe able to get at least 10ns (but it will mos= t likely be more). The exact cell name will depend upon the cell library yo= u are using. (For ARM libs, you'd want BUFXN or DLYXN).

For the instance names of the cells, add a pattern such as dont_touch to th= e instance name. E.g.

BUFX4 u_buf_1_dont_touch (.Y(t), .A(in)); BUFX4 u_buf_2_dont_touch (.Y(out), .A(t));

If you are using Design Compiler for synthesis, execute the following comma= nd after elaboration to prevent it from modifying them during synthesis:

set_dont_touch [get_cells -hier *dont_touch*]

If using RTL Compiler, you need to use set_attribute preserve.

Cheers, Jon