for all those who believe in ASICs....

My guess is that Xilinx does not prepare custome tests. Instead they select a handful from their pool of test vectors used to test the whole device. So the issue is how to decide which test vectors to use against a customer design: pretty simple really.....

One issue which I feel has been overlooked in the cost analysis is that yields are higher for easypath than they would be for the equivalent FPGA part.....

So I'd say that the cost savings come from both testing and yield improvements....

No?

With the very high margins as they as they are, and I suspect the majority of the other direct and indirect costs for all purposes fixed, I suspect that testing costs are a redherring as far as any significant cost variable which would signficantly impact end user price. IE for every dollar of revenue, testing costs are maybe a penny (or two). If you asked for untested unpackaged die or full wafers prorated by statistical yield, I suspect there isn't much of a savings to be offered given that the real price setters are margins, other direct costs, and indirect costs which remain unchanged.

I used to work for a semiconductor company. Test costs were sometimes very significant, as the test equipment was expensive. Some complex logic parts had long test times, and for one part I worked on the test cost was roughly a quarter of the selling price, and roughly half of the total cost.

Of course, this was an extreme example, and this was decades ago. I'm sure the business has changed. Still, I'm not convinced that test costs are quite as low as you assume.

-- Phil Hays

Nick,

Yes, and no. That is not what we do.

We take the customer's bit pattern, and use proprietary software to create a complete set of tests that test to a quality factor that is much better than we can for a generic FPGA, and far better than any ASIC test program can test for.

And yes, you figured it out: the yield for EasyPath(tm) is better.

Austin

John,

Not true. Test costs are not a red herring.

Look at the time spent in the socket of the tester, both at wafer sort, and at packaged parts.

Look at the cost of the tester (which is in the millions of $).

We are not talking about a second of time here, we are talking about running 'zillionz' (actual numbers are proprietary) of patterns at both wafer sort and more at packaged parts to get the quality factor that our generic FPGA customers demand.

Remember each test pattern is a configuration, which on a large part, takes time. The actual running of the pattern is insignificant to the time it takes to load.

Compare that with only a handful (again proprietary, but the image is entirely appropriate and accurate) of tests, which actually test to a better quality factor (coverage) for that application because the design is known, and only those resources used are tested.

That, and yield are the two factors which contribute to the cost savings to Xilinx that we can pass on to customers in the form of a lower price.

It is also the reason why we have no small parts in EasyPath(tm): small parts have far less test time, and they also have extremely good yield even for the generic versions.

Austin

about $576M. There are a few direct costs listed in that same report which probably are just under half of that which are fixed costs for buildings, IP, and other payments, dropping the remaining direct costs per dollar under $0.25. Not included are labor costs, or direct wafer cost payments, etc to be taken out of that 25 cents. I strongly suspect from that, testing isn't as much as a penny or two.

So, we know from the gross margins of the annual report, that testing isn't 50% or even 25% as you may have experienced in the past. I suspect the big changes over the last couple decades are investments like BIST style testing to facilitate screening without expensive testers driving full test coverage as we saw in the 1980's.

Two years ago, the marketing spin was "The Virtex-II EasyPath solution offers a 25% to 80% cost reduction with production quantity deliveries (thousands of units) in as little as 8-10 weeks". That level of discount based on test costs alone doesn't play with the numbers reported by the annual report. Most of that discount has to be single piece to volume discounts, or other incentives - not testing costs.

Austin, you mentioned a patent on Easypath, I went to look for it, but couldn't find anything.

Do you know if the patent has been approved and published yet? It normally takes some time to get it out.....

John,

The annual report includes CPLDs, FPGAs (all sizes), services, and storage.

Devil is in the details.

Austin

I think everyone understands that a) test costs are real, and significant but b) they are not 100% of the discounts offered in Easypath.

The rest is 'amortisation allocation' and simple marketing politics. What exact proportion ? - does it matter ?

However, you will never get a marketing spin merchant to admit that; they NEED something to pitch, so that ALL users do not ask for discounts :)

-jg

Nick C,

I thought it was issued, but I may be in error. That would make it "pending." Either that, or I can't find it either. Lots of Xilinx patents to crawl through...

Austin

Yep ... and and the Devil is in the spin. :)

My family is from the show me state .... and I'd like to see the numbers behind the spin that testing is responsible for a 25-80% savings over a 50K FPGA order converting to easypath.

Phil Hays wrote

A while back, Intel used to say that test costs were about the same as fabrication costs. I expect they meant the variable costs, not the (fixed) capital costs. And this was in the '80s, with a product which would not have had even a fraction of the built-in self-test possible in a big FPGA.

John,

Sorry can't do. That would require an NDA, and a reason.

Seems I can't convince you of anything.

That is OK, I have gotten over that.

Keep me honest,

Austin

-snip-

This thread has gotten much too esoteric and also too confrontational. It is really quite simple and intuitively obvious:

Everybody agrees that the manufacturing cost of chips grows overproportionally with die size. That's because, at a given defect density (=manufacturing quality standard), a larger die is more likely to contain a defect than a smaller die. Let's assume a percentage yield of 50% for a very large perfect die. The percentage yield for a 5 times smaller die would be much higher,

85% or more. (This can be proven mathematically). But we will also get that same higher percentage yield from the big chip when we test only those 20% of the chip area that are really needed by the user's design. (Believe it or not, the average design uses less than 20% of the real chip resources, even when the designer is using every CLB and BlockRAM and thinks the chip is really full. You can call that the curse of programmable logic and the reason for its higher cost than custom circuits. Lots of internal circuits are unused in any specific user implementation. But every design leaves different things unused.) Throw in less testing cost, and EasyPath becomes a good business proposition. We do not have to go "dumpster diving" to make money with it. It's all basic statistics and some sound reasoning. No need to analyze our Annual Report either. Peter Alfke

it would be interesting to take the many multi-million exec-pay packages, and the billion-dollar stock buyback programs, which are used to boost the stock artificially in order to trigger big bonus payouts; and divide them over the number of chips sold.

Wouldn't surprise me to learn that it's a dollar per chip sold, or even more...

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I'm trying hard not to be conrfontational. It's also intuitively obvious that 80% discounts do not materialize from reduced testing costs.

certainly agreed

Agreed. But a 70% increase in yield when silicon is a tiny fraction (5-20%) of the normal sales price (given high margins, fixed costs, labor, testing, etc totalling 80-95% of the cost structure) does not create an 80% discount. Maybe a 3-10% discount. That part of the math is intuitively obvious.

I don't disagree at all.

I've never suggested that.

That the 80% savings comes from testing is not sound reasoning. That it comes from other sources, like agressive competitive pricing to buy market share, I believe is sound reasoning. I have no problem is Xilinx stating that it wants to buy market share by dropping or eliminating it's high margin.

I've lost track of the number of NDA's I'm party too ... have no problem taking yet another bit of information to the grave. The reason is harder to come up with ... that would be your call.

When you can convince me that taking to zero an item which is less than

10% of the total pricing structure, will generate 25-80% cost savings to the customer, I will have seriously impaired facilities. Simply Amdhal's law applied to cost/price structures.

Even Peter's example changing yields from 50% to 85% only reduces the total price by a few percent. Consider Peters example with some additional numbers -- 50% yeild on a $100 wafer with 100 parts, is $2 for each good part in silicon costs, to which testing, packaging, fixed production costs, and gross margin is added bring the total price of each part to $100 as an example. Increasing yield to 85%, only drops the silicon cost to $1.18, which at most would be an $0.82 drop in silicon cost and make roughly a $1.00 change (or 1% of price) in price since all the other costs, such as testing, packaging, fixed production costs, and gross margins (R&D, admin/sales, and stock holder return) dominate the per unit price. Assuming that testing costs as much as raw die, then 80% reduced testing will only change the cost from $2 to $0.40, saving $1.60 which might impact the price by another $2. Thus, by Peters example, based on yield increases, and testing saved, the net expected benifit to the customer would be $3 out of $100, or a 3% savings.

Mr Toy, I have never claimed 80% saving from reducing the testing cost.

But I have shown, by a hypothetical example, that we can double the yield, and thus cut the EasyPath basic manufacturing cost in half. We can thus sell these parts for half price, while maintaining our usual margins.

You do not have to explain to us how we are running, or how we should be running our business. I have been an electronics engineer since 1957, and Xilinx has been quite successful in its 21-year history. When we need your advice, we'll let you know.

Peter Alfke, not ashamed to put his name under his writings.

Maybe not, but that is the standing reason presented, was it not?

Actually, that assumes that distribution of overhead costs and margin are proportional to die cost, which may well not be the case, and in fact it's likely they are proportional to total costs including packaging, support, and other overheads, which is the basis for probing the statements. It also ignores the additional direct higher NRE and costs of supporting an additional product with shipment volumes a tiny fraction of other FPGA sales.

I'm simply objecting that over simplified justifications for the market segment simply do not make sense as presented so far. Frankly Xilinx is free to do business as it pleases. As I and others are free to question and probe for understanding. We can agree to disagree.

Frankly, you did not ask for any advice, nor did I OFFER any. Nor have I questioned your employers success. When any person posts on any topic, including speculation of your employers market, product, business plan that is NOT an inventation for YOU to tell them to SHUT UP.

Posting under this handle HAS NEVER BEEN A QUESTION OF SHAME. Your continued personal attacks are however grossly shameful on your part, and shame to the wonderful reputation of your employer you mistakenly think you are protecting with your lack of civility.

John Bass