Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Vivado MIG says "Design entry" is VERILOG, how to change to VHDL?
With Vivado 2015.4, I'm trying to add DDR3 memory to a Microblaze design. I add the Memory Interface Generator to the block diagram, and double-click on it to configure it. The windows that comes up...
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8 years ago
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Simplify handling of SW accessible registers in FPGA
Save lots of work - Auto-generate register related code and documentation, and - Keep SW, FPGA and Documentation synchronized Register Wizard is now free :-) Register Wizard is now released as a...
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8 years ago
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CFP: 2016 Universal Technology Management Conference (UTMC) - USA
2016 Universal Technology Management Conference (UTMC) Bemidji State University, Minnesota, USA May 26-28, 2016 The event will be held over three days, with presentations delivered by res earchers...
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8 years ago
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How to define a counter whose width is big enough to hold integer 27?
Hi, I have a constant N = 27, how to define a counter whose width is big enough to hold integer 27? Or how to get a constant = log N? Where "log" is a logarithm with base 2. Thank you. Weng
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8 years ago
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Re: Call for Papers Reminder (extended): International MultiConference of Engineers and Computer Scientists (IMECS 2016)
Hey) My name is Tobias Casey. I am a freelance writer with more than 5 years of experience in content writing and blogging, currently employed by where I help them with their blog. Also, on a part...
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8 years ago
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Advanced VHDL Verification - Made simple - For anyone
VHDL testbenches very often need better structuring. We should strive for overview, modifiability, extendibility, maintainability and re-use. We are now posting 3 very easy to understand articles on...
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8 years ago
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what are the semantics of yosys $alu and $macc cells?
I'd like to know if I can implement them with single bit full adders and single bit mult cells only, or if I need additional primitives. (trying to guess the semantics from the logic ops in their...
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8 years ago
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Graduate Research Assistantship at the Department of Computer Engineering, Hallym University, Gangwon-do, Korea
Graduate Research Assistantship at the Department of Computer Engineering, Hallym University, Gangwon-do, Korea The Embedded System on Chip Lab ( of the Hallym University s eeks to recruit promising...
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8 years ago
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VQ44 recommended footprint
The Xilinx packaging documentation for the VQ44/VQG44 package (document PK0 12, v1.2, dataed 2004-06-18) doesn't contain a recommended PCB footprint. I n attempting to find such a footprint, Google...
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8 years ago
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How do I instantiate an FGEN instance for Atmels Figaro IDS in EDIF?
Specifically it's about how to specify the function to implement in the FGEN instance. this I have as the cell definition early in the file: [...] (cell fgen (cellType generic) (view fgen (viewType...
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8 years ago
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Sending multiple MSI interrupts via Xilinx "AXI Memory Mapped to PCIe" core
Hi, I wanted to prepare a small IP core able to serialize multiple interrupts as MSI interrupts handled by the Xilinx AXI MM 2 PCIe bridge. In the newest documentation ( ) it is stated that: *...
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8 years ago
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Where is a code example on how to use a floating multiplier on FPGA for VHDL-2008?
Hi, I need a full code example on how to use a floating multiplier on FPGA for VHDL-2008. What is the document name from XILINX? Jim's slides on floating multiplier are good, but not full and...
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8 years ago
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Synplify Identify with Microsemi FPGAs
Is anybody out there using Microsemi's Libero SoC and the bundled Synplfiy Identify? Identify is giving me problems: 1. It will not accept a depth of greater than 128 even when I ask for it 2. Gives...
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8 years ago
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EPM240T100C5N, LM2596, USB Blaster.
How to make it visible in QuartusII ? Pinout cpld ? How to solder it to pcb ? Links ?
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8 years ago
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Source control and ip cores
I'm looking for a peace of advice. Currently I use git for version control in my VHDL projects and I usually i nclude all .vhd files as well as .xdc constrains files in it. But I don't k now what I...
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8 years ago
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