6 years ago
add the Memory Interface Generator to the block diagram, and double-click
on it to configure it. The windows that comes up says that "It is very impo
rtant that the correct Vivado Project Options are selected", that Design En
try is set to VERILOG (sic), and "If any of these options are incorrect, pl
ease click on 'Cancel', change the Vivado Project Options, and restart MIG.
However, the Vivado Project Options shows that my target language is VHDL
. What do I actually have to do to convince MIG that Design Entry is VHDL?